12469038

Essentials of
Electronic Testing
Vishwani D. Agrawal
Michael L. Bushnell
Essentials of Test: Agrawal & Bushnell 1

Part I
INTRODUCTION TO
TESTING

VLSI Realization Process
Customer’s need
Determine requirements
Write specifications
Design synthesis and Verification
Test development
Fabrication
Manufacturing test
Chips to customer
Definitions
 Design synthesis: Given an I/O function, develop
a procedure to manufacture a device using
known materials and processes.
 Verification: Predictive analysis to ensure that
the synthesized design, when manufactured, will
perform the given I/O function.
 Test: A manufacturing step that ensures that the
physical device, manufactured from the
synthesized design, has no manufacturing
defect.

Real Tests
 Based on analyzable fault models, which
may not map on real defects.
 Incomplete coverage of modeled faults due
to high complexity.
 Some good chips are rejected. The
fraction (or percentage) of such chips is
called the yield loss.
 Some bad chips pass tests. The fraction
(or percentage) of bad chips among all
passing chips is called the defect level.
October 28, 2001 Essentials of Test: Agrawal & Bushnell 5

Costs of Testing
 Design for testability (DFT)
 Chip area overhead and yield reduction
 Performance overhead
 Software processes of test
 Test generation and fault simulation
 Test programming and debugging
 Manufacturing test
 Automatic test equipment (ATE) capital cost
 Test center operational cost

Present and Future*
1997 -2001 2003 - 2006
Feature size (micron) 0.25 - 0.15 0.13 - 0.10

Transistors/sq. cm 4 - 10M 18 - 39M
Pin count 100 - 900 160 - 1475
Clock rate (MHz) 200 - 730 530 - 1100
Power (Watts) 1.2 - 61 2 - 96
* SIA Roadmap, IEEE Spectrum, July 1999

Cost of Manufacturing
Testing in 2000AD
 0.5-1.0GHz, analog instruments,1,024
digital pins: ATE purchase price
 = $1.2M + 1,024 x $3,000 = $4.272M
 Running cost (five-year linear depreciation)
 = Depreciation + Maintenance + Operation
 = $0.854M + $0.085M + $0.5M
 = $1.439M/year
 Test cost (24 hour ATE operation)
 = $1.439M/(365 x 24 x 3,600)
 = 4.5 cents/second
Course Outline
 Part I:
 Basic concepts and definitions
 Test process and ATE
 Test economics and product quality
 Fault modeling
 Part II:
 Logic and fault simulation
 Combinational circuit ATPG
 Sequential circuit ATPG
 Memory test
 Analog test
 Delay test and IDDQ test
 Part III:
 Scan design
 BIST
 Boundary scan and analog test bus
 System test and core-based design
VLSI Testing Process
and Equipment

Testing Principle

Automatic Test
Equipment Components
 Consists of:
 Powerful computer
 Powerful 32-bit Digital Signal Processor
(DSP) for analog testing
 Test Program (written in high-level
language) running on the computer
 Probe Head (actually touches the bare
or packaged chip to perform fault
detection experiments)
 Probe Card or Membrane Probe
(contains electronics to measure signals
on chip pin or pad)

Characterization Test
 Worst-case test
 Choose test that passes/fails chips
 Select statistically significant sample of
chips
 Repeat test for every combination of 2+
environmental variables
 Plot results in Schmoo plot
 Diagnose and correct design errors
 Continue throughout production life of chips
to improve design and process to increase
yield

Schmoo Plot

Manufacturing Test
 Determines whether manufactured chip

meets specs
 Must cover high % of modeled faults
 Must minimize test time (to control cost)
 No fault diagnosis
 Tests every device on chip
 Test at speed of application or speed
guaranteed by supplier

Burn-in or Stress Test
 Process:
 Subject chips to high temperature & over-
voltage supply, while running production
tests
 Catches:
 Infant mortality cases – these are
damaged chips that will fail in the first 2
days of operation – causes bad devices to
actually fail before chips are shipped to
customers
 Freak failures – devices having same
failure mechanisms as reliable devices

Types of Manufacturing
Tests
 Wafer sort or probe test – done before
wafer is scribed and cut into chips
 Includes test site characterization –
specific test devices are checked with
specific patterns to measure:
 Gate threshold
 Polysilicon field threshold
 Poly sheet resistance, etc.
 Packaged device tests

Sub-types of Tests
 Parametric – measures electrical

properties of pin electronics – delay,
voltages, currents, etc. – fast and cheap
 Functional – used to cover very high % of
modeled faults – test every transistor and
wire in digital circuits – long and expensive
– main topic of tutorial

Two Different Meanings
of Functional Test
 ATE and Manufacturing World – any vectors

applied to cover high % of faults during
manufacturing test
 Automatic Test-Pattern Generation World –
testing with verification vectors, which
determine whether hardware matches its
specification – typically have low fault
coverage (< 70 %)

Test Specifications & Plan
 Test Specifications:
 Functional Characteristics
 Type of Device Under Test (DUT)
 Physical Constraints – Package, pin
numbers, etc.
 Environmental Characteristics – supply,
temperature, humidity, etc.
 Reliability – acceptance quality level
(defects/million), failure rate, etc.
 Test plan generated from specifications
 Type of test equipment to use
 Types of tests
 Fault coverage requirement
ADVANTEST Model
T6682 ATE

LTX FUSION HF ATE

Summary
 Parametric tests – determine whether pin electronics
system meets digital logic voltage, current, and delay
time specs
 Functional tests – determine whether internal
logic/analog sub-systems behave correctly
 ATE Cost Problems
 Pin inductance (expensive probing)
 Multi-GHz frequencies
 High pin count (1024)
 ATE Cost Reduction
 Multi-Site Testing
 DFT methods like Built-In Self-Test

Test Economics and
Product Quality

Economics of Design for
Testability (DFT)
 Consider life-cycle cost; DFT on chip may
impact the costs at board and system
levels.
 Weigh costs against benefits
 Cost examples: reduced yield due to area
overhead, yield loss due to non-functional
tests
 Benefit examples: Reduced ATE cost due to
self-test, inexpensive alternatives to burn-in
test

Benefits and Costs of DFT
Level Design Fabri- Manuf. Maintenance Diagnosis Service
and test cation Test test and repair interruption
Chips +/- + -
Boards +/- + - -
System +/- + - - - -
+ Cost increase
- Cost saving
+/- Cost increase may balance cost reduction

VLSI Chip Yield
 A manufacturing defect is a finite chip area
with electrically malfunctioning circuitry
caused by errors in the fabrication process.
 A chip with no manufacturing defect is called
a good chip.
 Fraction (or percentage) of good chips
produced in a manufacturing process is called
the yield. Yield is denoted by symbol Y.
 Cost of a chip:
Cost of fabricating and testing a wafer

--------------------------------------------------------------------
Yield x Number of chip sites on the wafer
Defect Level or Reject Ratio
 Defect level (DL) is the ratio of faulty
chips among the chips that pass tests.
 DL is measured as parts per million (ppm).
 DL is a measure of the effectiveness of
tests.
 DL is a quantitative measure of the
manufactured product quality. For
commercial VLSI chips a DL greater than
500 ppm is considered unacceptable.

Modified Yield Equation
 Three parameters:
 Fault density, f = average number of
stuck-at faults per unit chip area
 Fault clustering parameter, b
 Stuck-at fault coverage, T
 The modified yield equation:
Y (T ) = (1 + TAf / b) - b
Assuming that tests with 100% fault coverage
(T =1.0) remove all faulty chips,
Y = Y (1) = (1 + Af / b) - b

Defect Level
Y (T ) - Y (1)
DL (T ) = --------------------
Y (T )
b
( b + TAf )
= 1 - --------------------
b
( b + Af )
Where T is the fault coverage of tests,
Af is the average number of faults on the
chip of area A, b is the fault clustering
parameter. Af and b are determined by
test data analysis.
Example: SEMATECH Chip
 Bus interface controller ASIC fabricated
and tested at IBM, Burlington, Vermont
 116,000 equivalent (2-input NAND) gates
 304-pin package, 249 I/O
 Clock: 40MHz, some parts 50MHz
 0.45m CMOS, 3.3V, 9.4mm x 8.8mm area
 Full scan, 99.79% fault coverage
 Advantest 3381 ATE, 18,466 chips tested
at 2.5MHz test clock
 Data obtained courtesy of Phil Nigh (IBM)

Test Coverage from
Fault Simulator
Stuck-at fault coverage
Vector number

Measured Chip Fallout
Measured chip fallout
Vector number

Model Fitting
Chip fallout vs. fault coverage
Chip fallout and computed 1-Y (T )
Y (1) = 0.7623
Measured chip fallout
Y (T ) for Af = 2.1 and b = 0.083
Stuck-at fault coverage, T

Computed DL
237,700 ppm (Y = 76.23%)
Defect level in ppm
Stuck-at fault coverage (%)

Summary
 VLSI yield depends on two process parameters,
defect density (d ) and clustering parameter (a)
 Yield drops as chip area increases; low yield
means high cost
 Fault coverage measures the test quality
 Defect level (DL) or reject ratio is a measure of
chip quality
 DL can be determined by an analysis of test
data
 For high quality: DL < 500 ppm, fault coverage
~ 99%

Fault Modeling

Why Model Faults?
 I/O function tests inadequate for

manufacturing (functionality versus
component and interconnect testing)
 Real defects (often mechanical) too
numerous and often not analyzable
 A fault model identifies targets for testing
 A fault model makes analysis possible
 Effectiveness measurable by experiments

Some Real Defects in Chips
 Processing defects
 Missing contact windows
 Parasitic transistors
 Oxide breakdown
 . . .
 Material defects
 Bulk defects (cracks, crystal imperfections)
 Surface impurities (ion migration)
 . . .
 Time-dependent failures
 Dielectric breakdown
 Electromigration
 . . .
 Packaging failures
 Contact degradation
 Seal leaks
 . . .
Ref.: M. J. Howes and D. V. Morgan, Reliability and Degradation -

Semiconductor Devices and Circuits, Wiley, 1981.
Observed PCB Defects
Defect classes Occurrence frequency (%)
Shorts 51
Opens 1
Missing components 6
Wrong components 13
Reversed components 6
Bent leads 8
Analog specifications 5
Digital logic 5
Performance (timing) 5
Ref.: J. Bateson, In-Circuit Testing, Van Nostrand Reinhold, 1985.

Common Fault Models
 Single stuck-at faults
 Transistor open and short faults
 Memory faults
 PLA faults (stuck-at, cross-point, bridging)
 Functional faults (processors)
 Delay faults (transition, path)
 Analog faults
 For more examples, see Section 4.4 (p. 60-
70) of the book.

Single Stuck-at Fault
 Three properties define a single stuck-at fault
 Only one line is faulty
 The faulty line is permanently set to 0 or 1
 The fault can be at an input or output of a gate
 Example: XOR circuit has 12 fault sites ( ) and
24 single stuck-at faults
Faulty circuit value
Good circuit value
c j
s-a-0 0(1)
a d 1(0)
1 g h
z
0 1 i
b e 1
f k
Test vector for h s-a-0 fault
Fault Equivalence
 Number of fault sites in a Boolean gate circuit
= #PI + #gates + #(fanout branches).
 Fault equivalence: Two faults f1 and f2 are
equivalent if all tests that detect f1 also
detect f2.
 If faults f1 and f2 are equivalent then the
corresponding faulty functions are identical.
 Fault collapsing: All single faults of a logic
circuits can be divided into disjoint
equivalence subsets, where all faults in a
subset are mutually equivalent. A collapsed
fault set contains one fault from each
equivalence subset.

Equivalence Rules
sa0 sa0
sa1 sa1
sa0 sa1 sa0 sa1 WIRE
sa0 sa1 sa0 sa1
AND OR
sa0 sa1 sa0 sa1
sa0 sa1
NOT
sa1 sa0
sa0 sa1 sa0 sa1

sa0 sa1 sa0 sa1 sa0
NAND NOR
sa1
sa0
sa0 sa1 sa0 sa1
sa1
sa0
FANOUT sa1
Equivalence Example
sa0 sa1
Faults in red
sa0 sa1 removed by
sa0 sa1 equivalence
collapsing
sa0 sa1 sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1 sa0 sa1
sa0 sa1
sa0 sa1 sa0 sa1

sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
20
Collapse ratio = ----- = 0.625
32
Fault Dominance
 If all tests of some fault F1 detect another fault
F2, then F2 is said to dominate F1.
 Dominance fault collapsing: If fault F2
dominates F1, then F2 is removed from the
fault list.
 When dominance fault collapsing is used, it is
sufficient to consider only the input faults of
Boolean gates. See the next example.
 In a tree circuit (without fanouts) PI faults form
a dominance collaped fault set.
 If two faults dominate each other then they are
equivalent.

Dominance Example
All tests of F2
F1
s-a-1 001
F2
s-a-1 110 010
000
101 011
100
s-a-1 Only test of F1
s-a-1
s-a-1
s-a-0
A dominance collapsed fault set

Checkpoints
 Primary inputs and fanout branches of a
combinational circuit are called checkpoints.
 Checkpoint theorem: A test set that detects
all single (multiple) stuck-at faults on all
checkpoints of a combinational circuit, also
detects all single (multiple) stuck-at faults in
that circuit.
Total fault sites = 16
Checkpoints ( ) = 10

Classes of Stuck-at Faults
 Following classes of single stuck-at faults are
identified by fault simulators:
 Potentially-detectable fault -- Test produces an
unknown (X) state at PO; detection is
probabilistic, usually with 50% probability.
 Initialization fault -- Fault prevents initialization of
the faulty circuit; can be detected as a potentially-
detectable fault.
 Hyperactive fault -- Fault induces much internal
signal activity without reaching PO.
 Redundant fault -- No test exists for the fault.
 Untestable fault -- Test generator is unable to find
a test.

Summary
 Fault models are analyzable approximations of
defects and are essential for a test
methodology.
 For digital logic single stuck-at fault model
offers best advantage of tools and experience.
 Many other faults (bridging, stuck-open and
multiple stuck-at) are largely covered by
stuck-at fault tests.
 Stuck-short and delay faults and technology-
dependent faults require special tests.
 Memory and analog circuits need other
specialized fault models and tests.

Part II
TEST METHODS
Logic Simulation

Simulation Defined
 Definition: Simulation refers to modeling of a
design, its function and performance.
 A software simulator is a computer program;
an emulator is a hardware simulator.
 Simulation is used for design verification:
 Validate assumptions
 Verify logic
 Verify performance (timing)
 Types of simulation:
 Logic or switch level
 Timing
 Circuit
 Fault

Simulation for Verification
Specification
Synthesis
Response Design Design

analysis changes (netlist)
Computed True-value
Input stimuli
responses simulation

Modeling for Simulation
 Modules, blocks or components described by
 Input/output (I/O) function
 Delays associated with I/O signals
 Examples: binary adder, Boolean gates, FET,
resistors and capacitors
 Interconnects represent
 ideal signal carriers, or
 ideal electrical conductors
 Netlist: a format (or language) that describes
a design as an interconnection of modules.
Netlist may use hierarchy.

Example: A Full-Adder
HA;
c
inputs: a, b;
a
e outputs: c, f;
AND: A1, (a, b), (c);
d f AND: A2, (d, e), (f);
b OR: O1, (a, b), (d);
HA NOT: N1, (c), (e);
FA;
A D inputs: A, B, C;
Carry
B
HA1 E F outputs: Carry, Sum;
C
HA2 Sum HA: HA1, (A, B), (D, E);
HA: HA2, (E, C), (F, Sum);
OR: O2, (D, F), (Carry);

Logic Model of MOS Circuit
pMOS FETs VDD
a Da
a Dc c
Ca b Db
c
b Cc
Da and Db are
Cb interconnect or
nMOS FETs
propagation delays
Dc is inertial delay
Ca , Cb and Cc are of gate
parasitic capacitances

Options for Inertial Delay
(simulation of a NAND gate)
Transient
a
region
Inputs
c (CMOS)
c (zero delay)
Logic simulation
c (unit delay)
X
c (multiple delay) rise=5, fall=5
Unknown (X)
c (minmax delay) min =2, max =5
0 5 Time units

Signal States
 Two-states (0, 1) can be used for purely
combinational logic with zero-delay.
 Three-states (0, 1, X) are essential for
timing hazards and for sequential logic
initialization.
 Four-states (0, 1, X, Z) are essential for MOS
devices. See example below.
 Analog signals are used for exact timing of
digital logic and for analog circuits.
Z
(hold previous value)
0
0
Modeling Levels
Modeling Circuit Signal Timing Application
level description values
Architectural
Function, Programming 0, 1 Clock and functional
behavior, RTL language-like HDL boundary verification
Logic Connectivity of 0, 1, X Zero-delay Logic

Boolean gates, unit-delay, verification
and Z multiple-
flip-flops and and test
transistors delay
Switch Transistor size 0, 1 Zero-delay Logic

and connectivity, and X verification
node capacitances
Timing Transistor technology Analog Fine-grain Timing

data, connectivity, voltage timing verification
node capacitances
Circuit Continuous Digital timing
Tech. Data, active/ Analog
time and analog
passive component voltage,
circuit
connectivity current
verification
True-Value Simulation
Algorithms
 Compiled-code simulation
 Applicable to zero-delay combinational logic
 Also used for cycle-accurate synchronous sequential
circuits for logic verification
 Efficient for highly active circuits, but inefficient for
low-activity circuits
 High-level (e.g., C language) models can be used
 Event-driven simulation
 Only gates or modules with input events are
evaluated (event means a signal change)
 Delays can be accurately simulated for timing
verification
 Efficient for low-activity circuits
 Can be extended for fault simulation

Compiled-Code Algorithm
 Step 1: Levelize combinational logic and
encode in a compilable programming language
 Step 2: Initialize internal state variables (flip-
flops)
 Step 3: For each input vector
 Set primary input variables
 Repeat (until steady-state or max. iterations)
 Execute compiled code
 Report or save computed variables

Event-Driven Algorithm
(Example)
Scheduled Activity
events list
a =1 e =1 t=0 c=0 d, e
c =1 0 2
1
g =1
2
2 2 d = 1, e = 0 f, g
d=0
Time stack
3
4 f =0
b =1 4 g=0
5
g 6 f=1 g
0 4 8
Time, t 7
8 g=1
Efficiency of Event-
driven Simulator
 Simulates events (value changes) only
 Speed up over compiled-code can be ten
times or more; in large logic circuits about
0.1 to 10% gates become active for an input
change
Steady 0
Steady 0 Large logic
block without
(no event)
0 to 1 event activity

Summary
 Logic or true-value simulators are essential
tools for design verification.
 Verification vectors and expected responses
are generated (often manually) from
specifications.
 A logic simulator can be implemented using
either compiled-code or event-driven method.
 Per vector complexity of a logic simulator is
approximately linear in circuit size.
 Modeling level determines the evaluation
procedures used in the simulator.

Fault Simulation

Problem and Motivation
 Fault simulation Problem: Given
 A circuit
 A sequence of test vectors
 A fault model
 Determine
 Fault coverage - fraction (or percentage) of
modeled faults detected by test vectors
 Set of undetected faults
 Motivation
 Determine test quality and in turn product quality
 Find undetected fault targets to improve tests

Fault simulator in a VLSI
Design Process
Verified design Verification
netlist input stimuli
Fault simulator Test vectors
Modeled Remove Test Delete

fault list tested faults compactor vectors
Fault Low Test

coverage generator Add vectors
?
Adequate
Stop
Fault Simulation Scenario
 Circuit model: mixed-level
 Mostly logic with some switch-level for high-
impedance (Z) and bidirectional signals
 High-level models (memory, etc.) with pin faults
 Signal states: logic
 Two (0, 1) or three (0, 1, X) states for purely
Boolean logic circuits
 Four states (0, 1, X, Z) for sequential MOS circuits
 Timing:
 Zero-delay for combinational and synchronous
circuits
 Mostly unit-delay for circuits with feedback

Fault Simulation Scenario
(continued)
 Faults:
 Mostly single stuck-at faults
 Sometimes stuck-open, transition, and path-delay
faults; analog circuit fault simulators are not yet in
common use
 Equivalence fault collapsing of single stuck-at
faults
 Fault-dropping -- a fault once detected is dropped
from consideration as more vectors are simulated;
fault-dropping may be suppressed for diagnosis
 Fault sampling -- a random sample of faults is
simulated when the circuit is large

Fault Simulation
Algorithms
 Serial
 Parallel
 Deductive
 Concurrent
 Differential

Serial Algorithm
 Algorithm: Simulate fault-free circuit and save
responses. Repeat following steps for each
fault in the fault list:
 Modify netlist by injecting one fault
 Simulate modified netlist, vector by vector,
comparing responses with saved responses
 If response differs, report fault detection and
suspend simulation of remaining vectors
 Advantages:
 Easy to implement; needs only a true-value
simulator, less memory
 Most faults, including analog faults, can be
simulated

Serial Algorithm (Cont.)
 Disadvantage: Much repeated computation;
CPU time prohibitive for VLSI circuits
 Alternative: Simulate many faults together
Test vectors Fault-free circuit Comparator f1 detected?
Circuit with fault f1

Comparator f2 detected?
Circuit with fault f2
Comparator fn detected?
Circuit with fault fn

Parallel Fault Simulation
 Compiled-code method; best with two-
states (0,1)
 Exploits inherent bit-parallelism of logic
operations on computer words
 Storage: one word per line for two-state
simulation
 Multi-pass simulation: Each pass simulates
w-1 new faults, where w is the machine
word length
 Speed up over serial method ~ w-1
 Not suitable for circuits with timing-critical
and non-Boolean logic

Parallel Fault Sim. Example
Bit 0: fault-free circuit
Bit 1: circuit with c s-a-0
Bit 2: circuit with f s-a-1
1 1 1
c s-a-0 detected
a 1 0 1
1 1 1 1 0 1
b e 1 0 1
c s-a-0
g
0 0 0
d f s-a-1 0 0 1

Deductive Fault Simulation
 One-pass simulation
 Each line k contains a list Lk of faults
detectable on k
 Following true-value simulation of each
vector, fault lists of all gate output lines
are updated using set-theoretic rules,
signal values, and gate input fault lists
 PO fault lists provide detection data
 Limitations:
 Set-theoretic rules difficult to derive for non-
Boolean gates
 Gate delays are difficult to use

Concurrent Fault Simulation
 Event-driven simulation of fault-free circuit and
only those parts of the faulty circuit that differ in
signal states from the fault-free circuit.
 A list per gate containing copies of the gate from
all faulty circuits in which this gate differs. List
element contains fault ID, gate input and output
values and internal states, if any.
 All events of fault-free and all faulty circuits are
implicitly simulated.
 Faults can be simulated in any modeling style or
detail supported in true-value simulation (offers
most flexibility.)
 Faster than other methods, but uses most
memory.
Conc. Fault Sim. Example
a0 b0 c0 e0
0 1 1 1
0 0 0 0
1 0 0 1
1
a 1 1
1 1
b 1 e 1
c 1
1 g
0
0
d
1 0
f a0 b0 c0 e0
0 0 0 0
0 1 0 0
0 1 0 0
1 1 1
0 1 1
b0 d0 f1 0
g 1 1
d0
0 1
f1
0 1 1 1
0
Fault Sampling
 A randomly selected subset (sample) of
faults is simulated.
 Measured coverage in the sample is used
to estimate fault coverage in the entire
circuit.
 Advantage: Saving in computing resources
(CPU time and memory.)
 Disadvantage: Limited data on undetected
faults.

Random Sampling Model
Detected Undetected
fault fault
All faults with

a fixed but Random
unknown picking
coverage
Np = total number of faults Ns = sample size
(population size) Ns << Np
C = fault coverage (unknown) c = sample coverage
(a random variable)

Probability Density of
Sample Coverage, c
(x--C )2
-- ------------
1 2s 2
p (x ) = Prob(x < c < x +dx ) = -------------- e
s (2 p) 1/2
2 C (1 - C)
Variance, s = ------------
Ns Sampling
p (x )
s s
error
Mean = C
x
C -3s C x C +3s 1.0
Sample coverage
Sampling Error Bounds
C (1 - C ) 1/2
|x-C|=3 [ -------------- ]
N s
Solving the quadratic equation for C, we get the
3-sigma (99.7% confidence) estimate:
4.5
C 3s = x  ------- [1 + 0.44 Ns x (1 - x )]1/2
Ns
Where Ns is sample size and x is the measured fault
coverage in the sample.
Example: A circuit with 39,096 faults has an actual
fault coverage of 87.1%. The measured coverage in
a random sample of 1,000 faults is 88.7%. The above
formula gives an estimate of 88.7% 3%. CPU time for 
sample simulation was about 10% of that for all faults.
Summary
 Fault simulator is an essential tool for test development.
 Concurrent fault simulation algorithm offers the best
choice.
 For restricted class of circuits (combinational and
synchronous sequential with only Boolean primitives),
differential algorithm can provide better speed and
memory efficiency (Section 5.5.6.)
 For large circuits, the accuracy of random fault sampling
only depends on the sample size (1,000 to 2,000 faults)
and not on the circuit size. The method has significant
advantages in reducing CPU time and memory needs of
the simulator.

Combinational
Automatic Test-pattern
Generation

Functional vs. Structural
ATPG

Carry Circuit

Functional vs. Structural
(Continued)
 Functional ATPG – generate complete set of tests for
circuit input-output combinations
 129 inputs, 65 outputs:
 2129 = 680,564,733,841,876,926,926,749,
214,863,536,422,912 patterns
 Using 1 GHz ATE, would take 2.15 x 1022 years
 Structural test:
 No redundant adder hardware, 64 bit slices
 Each with 27 faults (using fault equivalence)
 At most 64 x 27 = 1728 faults (tests)
 Takes 0.000001728 s on 1 GHz ATE
 Designer gives small set of functional tests – augment
with structural tests to boost coverage to 98+ %

Definition of Automatic
Test-Pattern Generator
 Operations on digital hardware:

 Inject fault into circuit modeled in computer
 Use various ways to activate and propagate
fault effect through hardware to circuit output
 Output flips from expected to faulty signal

Circuit and Binary
Decision Tree

Algorithm Completeness
 Definition: Algorithm is complete if it
ultimately can search entire binary
decision tree, as needed, to generate a
test
 Untestable fault – no test for it even after
entire tree searched
 Combinational circuits only – untestable
faults are redundant, showing the
presence of unnecessary hardware

Algebras: Roth’s 5-Valued
and Muth’s 9-Valued
Good Failing
Symbol Meaning Machine Machine
D 1/0 0 1
D 0/1 1 0 Roth’s
0 0/0 0 0 Algebra
1 1/1 1 1
X X/X X X
G0 0/X 0 X
G1 1/X 1 X Muth’s
F0 X/0 X 0 Additions
F1 X/1 X 1

Random-Pattern Generation
 Flow chart for

method
 Use to get
tests for 60-
80% of faults,
then switch
to D-algorithm
or other ATPG
for rest

Path Sensitization Method
Circuit Example
1 Fault Sensitization
2 Fault Propagation
3 Line Justification

Circuit Example
 Try path f – h – k – L blocked at j, since
there is no way to justify the 1 on i
1 D
D D
1 D
D 0
1

Circuit Example
 Try simultaneous paths f – h – k – L and
g – i – j – k – L blocked at k because
D-frontier (chain of D or D) disappears
1 D
D 1
1
D D
D

Circuit Example
 Final try: path g – i – j – k – L – test found!
0
0 D
1 D
D D D
1
1

History of Algorithm
Speedups
Algorithm Est. speedup over D-ALG Year
(normalized to D-ALG time)
D-ALG 1 1966
PODEM 7 1981
FAN 23 1983
TOPS 292 1987
SOCRATES 1574 † ATPG System 1988
Waicukauski et al. 2189 † ATPG System 1990
EST 8765 † ATPG System 1991
TRAN 3005 † ATPG System 1993
Recursive learning 485 1995
Tafertshofer et al. 25057 1997

Analog Fault Modeling
Impractical for Logic ATPG
 Huge # of different possible analog faults
in digital circuit
 Exponential complexity of ATPG algorithm
– a 20 flip-flop circuit can take days of
computing
 Cannot afford to go to a lower-level
model
 Most test-pattern generators for digital
circuits cannot even model at the
transistor switch level (see textbook for 5
examples of switch-level ATPG)

Fault Cone and D-frontier
 Fault Cone -- Set of hardware affected by fault
 D-frontier – Set of gates closest to POs with fault
effect(s) at input(s)
D-frontier
Fault Cone

Forward Implication
 Results in logic gate inputs
that are significantly
labeled so that output is
uniquely determined
 AND gate forward
implication table:

Backward Implication
 Unique determination of all gate inputs when the
gate output and some of the inputs are given

Implication Stack after
Backtrack
Unexplored
Present Assignment 0 E 1
Searched and Infeasible
B B
0 1 0 1
F F F
0 1 0 1 0 1

Branch-and-Bound Search
 Efficiently searches binary search tree

 Branching – At each tree level, selects
which input variable to set to what value
 Bounding – Avoids exploring large tree
portions by artificially restricting search
decision choices
 Complete exploration is impractical
 Uses heuristics

Sequential Automatic
Test-pattern Generation

Sequential Circuits
 A sequential circuit has memory in addition
to combinational logic.
 Test for a fault in a sequential circuit is a
sequence of vectors, which
 Initializes the circuit to a known state
 Activates the fault, and
 Propagates the fault effect to a primary
output
 Methods of sequential circuit ATPG
 Time-frame expansion methods
 Simulation-based methods

Concept of Time-Frames
 If the test sequence for a single stuck-at
fault contains n vectors,
 Replicate combinational logic block n times
 Place fault in each block
 Generate a test for the multiple stuck-at fault
using combinational ATPG with 9-valued logic
Vector -n+1 Vector -1 Vector 0
Fault
Unknown
Time- State Time- Time- Next
or given
frame variables frame frame state
Init. state
-n+1 -1 0
Comb.
block PO -n+1 PO -1 PO 0
Example for Logic Systems
FF1
B
A FF2
s-a-1

Nine-Valued Logic (Muth)
0,1, 1/0, 0/1, 1/X, 0/X, X/0, X/1, X
A 0 A X
s-a-1 s-a-1
0/1 X/1
X 0/X 0/X
FF1 FF1
X 0/1 X/1
FF2 FF2
B X B 0/1
Time-frame -1 Time-frame 0

Implementation of ATPG
 Select a PO for fault detection based on drivability
analysis.
 Place a logic value, 1/0 or 0/1, depending on fault
type and number of inversions.
 Justify the output value from PIs, considering all
necessary paths and adding backward time-frames.
 If justification is impossible, then use drivability to
select another PO and repeat justification.
 If the procedure fails for all reachable POs, then the
fault is untestable.
 If 1/0 or 0/1 cannot be justified at any PO, but 1/X or
0/X can be justified, the the fault is potentially
detectable.

Complexity of ATPG
 Synchronous circuit -- All flip-flops controlled by clocks;
PI and PO synchronized with clock:
 Cycle-free circuit – No feedback among flip-flops:
Test generation for a fault needs no more than
dseq + 1 time-frames, where dseq is the
sequential depth.
 Cyclic circuit – Contains feedback among flip-
flops: May need 9Nff time-frames, where Nff is the
number of flip-flops.
 Asynchronous circuit – Higher complexity!
Smax Time- Time- S3 Time- S2 Time- S1 Time- S0

Frame Frame Frame Frame Frame
max-1 max-2 -2 -1 0
max = Number of distinct vectors with 9-valued elements = 9Nff

Cycle-Free Circuits
 Characterized by absence of cycles among

flip-flops and a sequential depth, dseq.
 dseq is the maximum number of flip-flops
on any path between PI and PO.
 Both good and faulty circuits are
initializable.
 Test sequence length for a fault is bounded
by dseq + 1.

Cycle-Free Example
Circuit
F2
F3
F1
3
Level = 1 F2
2
s - graph
F1 F3 dseq = 3
Level = 1 3
All faults are testable. See Example 8.6.

Cyclic Circuit Example
Modulo-3 counter
Z
CNT F2
F1
s - graph
F1 F2

Adding Initializing Hardware
Initializable modulo-3 counter
Z
CNT F2
F1
s-a-0
s-a-1
CLR
s-a-1 s-a-1 Untestable fault
Potentially detectable fault
s - graph
F1 F2

Benchmark Circuits
Circuit s1196 s1238 s1488 s1494
PI 14 14 8 8
PO 14 14 19 19
FF 18 18 6 6
Gates 529 508 653 647
Structure Cycle-free Cycle-free Cyclic Cyclic
Seq. depth 4 4 -- --
Total faults 1242 1355 1486 1506
Detected faults 1239 1283 1384 1379
Potentially detected faults 0 0 2 2
Untestable faults 3 72 26 30
Abandoned faults 0 0 76 97
Fault coverage (%) 99.8 94.7 93.1 91.6
Fault efficiency (%) 100.0 100.0 94.8 93.4
Max. sequence length 3 3 24 28
Total test vectors 313 308 525 559
Gentest CPU s (Sparc 2) 10 15 19941 19183

Simulation-based ATPG
 Difficulties with time-frame method:
 Long initialization sequence
 Impossible initialization with three-valued logic
(Section 5.3.4)
 Circuit modeling limitations
 Timing problems – tests can cause races/hazards
 High complexity
 Inadequacy for asynchronous circuits
 Advantages of simulation-based methods
 Advanced fault simulation technology
 Accurate simulation model exists for verification
 Variety of tests – functional, heuristic, random
 Used since early 1960s

Using Fault Simulator
Vector source:
Generate Functional (test-bench),
new trial Heuristic (walking 1, etc.),
vectors Weighted random,
random
No
Trial vectors
Stopping
Yes criteria (fault Fault Fault
coverage, CPU
simulator list
time limit, etc.)
satisfied? Restore
Update
circuit
fault
state
list
New faults Yes Test
Stop No
detected? Append vectors
vectors

Background
 Seshu and Freeman, 1962, Asynchronous circuits,
parallel fault simulator, single-input changes vectors.
 Breuer, 1971, Random sequences, sequential circuits
 Agrawal and Agrawal, 1972, Random vectors followed
by D-algorithm, combinational circuits.
 Shuler, et al., 1975, Concurrent fault simulator, random
vectors, sequential circuits.
 Parker, 1976, Adaptive random vectors, combinational
circuits.
 Agrawal, Cheng and Agrawal, 1989, Directed search
with cost-function, concurrent fault simulator,
sequential circuits.
 Srinivas and Patnaik, 1993, Genetic algorithms; Saab,
et al., 1996; Corno, et al., 1996; Rudnick, et al., 1997;
Hsiao, et al., 1997.

Genetic Algorithms (GAs)
 Theory of evolution by natural selection (Darwin, 1809-82.)
 C. R. Darwin, On the Origin of Species by Means of Natural
Selection, London: John Murray, 1859.
 J. H. Holland, Adaptation in Natural and Artificial Systems,
Ann Arbor: University of Michigan Press, 1975.
 D. E. Goldberg, Genetic Algorithms in Search,
Optimization, and Machine Learning, Reading,
Massachusetts: Addison-Wesley, 1989.
 P. Mazumder and E. M. Rudnick, Genetic Algorithms for
VLSI Design, Layout and Test Automation, Upper Saddle
River, New Jersey, Prentice Hall PTR, 1999.
 Basic Idea: Population improves with each generation.
 Population
 Fitness criteria
 Regeneration rules

Strategate Results
s1423 s5378 s35932
Total faults 1,515 4,603 39,094
Detected faults 1,414 3,639 35,100
Fault coverage 93.3% 79.1% 89.8%
Test vectors 3,943 11,571 257
CPU time 1.3 hrs. 37.8 hrs. 10.2 hrs.

HP J200 256MB
Ref.: M. S. Hsiao, E. M. Rudnick and J. H. Patel, “Dynamic State

Traversal for Sequential Circuit Test Generation,” ACM Trans.
on Design Automation of Electronic Systems (TODAES), vol. 5,
no. 3, July 2000.

Summary
 Combinational ATPG algorithms are extended:
 Time-frame expansion unrolls time as combinational array
 Nine-valued logic system
 Justification via backward time
 Cycle-free circuits:
 Require at most dseq time-frames
 Always initializable
 Cyclic circuits:
 May need 9Nff time-frames
 Circuit must be initializable
 Partial scan can make circuit cycle-free (Chapter 14)
 Asynchronous circuits:
 High complexity
 Low coverage and unreliable tests
 Simulation-based methods are more useful (Section 8.3)

Memory Test

Memory Cells Per Chip

Test Time in Seconds
(Memory Size n Bits)
Size Number of Test Algorithm Operations

n n n X log2n n3/2 n2
1 Mb 0.06 1.26 64.5 18.3 hr

4 Mb 0.25 5.54 515.4 293.2 hr
16 Mb 1.01 24.16 1.2 hr 4691.3 hr
64 Mb 4.03 104.7 9.2 hr 75060.0 hr
256 Mb 16.11 451.0 73.3 hr 1200959.9 hr
1 Gb 64.43 1932.8 586.4 hr 19215358.4 hr
2 Gb 128.9 3994.4 1658.6 hr 76861433.7 hr

March Test Notation
 r -- Read a memory location
 w -- Write a memory location
 r0 -- Read a 0 from a memory location
 r1 -- Read a 1 from a memory location
 w0 -- Write a 0 to a memory location
 w1 -- Write a 1 to a memory location
 -- Write a 1 to a cell containing 0
 -- Write a 0 to a cell containing 1
March Test Notation
(Continued)
 -- Complement the cell contents
 -- Increasing memory addressing
 -- Decreasing memory addressing
 -- Either increasing or decreasing

MATS+ March Test
M0: { March element (w0) }
for cell := 0 to n - 1 (or any other order) do
write 0 to A [cell];
M1: { March element (r0, w1) }
for cell := 0 to n - 1 do
read A [cell]; { Expected value = 0}
M2: {March element (r1, w0) }
for cell := n – 1 down to 0 do
read A [cell]; { Expected value = 1 }

Reduced Functional
Faults
Fault
SAF Stuck-at fault
TF Transition fault
CF Coupling fault
NPSF Neighborhood Pattern Sensitive fault

Transition Faults
 Cell fails to make 0 1 or 1 0 transition
 Condition: Each cell must undergo a transition

and a transition, and be read after such,
before undergoing any further transitions.
 < /0>, < /1>
< /0> transition fault

Coupling Faults
 Coupling Fault (CF): Transition in bit j causes
unwanted change in bit i
 2-Coupling Fault: Involves 2 cells, special case of
k-Coupling Fault
 Must restrict k cells to make practical
 Inversion and Idempotent CFs -- special cases of
2-Coupling Faults
 Bridging and State Coupling Faults involve any #
of cells, caused by logic level
 Dynamic Coupling Fault (CFdyn) -- Read or write
on j forces i to 0 or 1

Idempotent Coupling
Faults (CFid)
 or transition in j sets cell i to 0 or 1
 Condition: For all coupled faults, each should be
read after a series of possible CFids may have
happened, such that the sensitized CFids do not
mask each other.
 Asymmetric: coupled cell only does or
 Symmetric: coupled cell does both due to fault
 < ; 0>, < ; 1>, < ; 0>, < ; 1>

Address Decoder Faults
 Address decoding error assumptions:
 Decoder does not become sequential
 Same behavior during both read & write
 Multiple ADFs must be tested for
 Decoders have CMOS stuck-open faults

Fault Modeling Example
SA1 gg SA1+SCF
ABF
ABF
SCF
SA0
ABF
Fault Hierarchy

Fault Frequency
 Obtained with Scanning Electron Microscope
 CFin and TF faults rarely occurred
Cluster # Devices Fault class

0 714 Stuck-at and Total failure
1 169 Stuck-open
2 18 Idempotent coupling
3 9 State coupling
4 8 ?
5 5 ?
7 26 Data retention
-- -- ?
14 2 ?
Functional RAM Testing
with March Tests
 March Tests can detect AFs -- NPSF Tests
Cannot
 Conditions for AF detection:
 Need ( r x, w x)
 Need ( r x, w x)
 In the following March tests, addressing
orders can be interchanged

Irredundant March Test
Summary
Algorithm SAF AF TF CF CF CF SCF Linked
in id dyn Faults
MATS All Some
MATS+ All All
MATS++ All All All
MARCH X All All All All
MARCH C— All All All All All All All
MARCH A All All All All Some
MARCH Y All All All All Some
MARCH B All All All All Some

MATS+ Example
Cell (2, 1) SA1 Fault
MATS+:
{ M0: (w0); M1: (r0, w1); M2: (r1, w0) }

Memory Testing
Summary
 Multiple fault models are essential

 Combination of tests is essential:
 March – SRAM and DRAM
 NPSF -- DRAM
 DC Parametric -- Both
 AC Parametric -- Both
 Inductive Fault Analysis is now required

Analog Test

Mixed-Signal Testing
Problem

Differences from Digital
Testing
 Size not a problem – at most 100 components
 Much harder analog device modeling
 No widely-accepted analog fault model
 Infinite signal range
 Tolerances depend on process and
measurement error
 Tester (ATE) introduces measurement error
 Digital / analog substrate coupling noise
 Absolute component tolerances +/- 20%,
relative +/- 0.1%
 Multiple analog fault model mandatory
 No unique signal flow direction
Present-Day Analog
Testing Methods
 Specification-based (functional) tests
 Main method for analog – tractable and
does not need an analog fault model
 Intractable for digital -- # tests is huge
 Structural ATPG – used for digital, just
beginning to be used for analog (exists)
 Separate test for functionality and timing
not possible in analog circuit
 Possible in digital circuit

Definitions
 ADC – A/D converter
 ATE – Automatic Test Equipment
 DAC – D/A converter
 DFT – Discrete Fourier Transform
 DUT – Device-Under-Test
 FFT – Fast Fourier Transform
 Glitch Area -- area in DAC output of glitching
pulses
 Jitter – Low-level electrical noise – corrupts
LSB’s, especially prevalent on converter
clocking circuits
 ks/s – Kilo-samples/sec
More Definitions
 LSB -- Least Significant Bit (of converter)
 Measurement – Result of measuring O/P
analog parameter and quantifying it
 Measurement Error – Introduced by
measurement process
 Non-Deterministic Device – All analog
circuit measurements are not repeatable
due to DUT or tester measurement noise
 Phase-Locked-Loop – Clock circuit with
feedback to keep desired signal phase
 Settling Time -- Time for DAC
reconstruction filter to settle
 Test – Combination of analog stimulus,
measurement of voltage or current, with a
measurement error tolerance
DSP Tester Concept
© 1987 IEEE

Waveform Synthesis
© 1987 IEEE
Needs sin x / x (sinc) correction – Finite

sample width

Waveform Sampling
© 1987 IEEE
Sampling rate > 100 ks/s

ATE Clock Generator
WS = waveform source WM = waveform measurement

A/D and D/A Test
Parameters
 A/D -- Uncertain map from input domain voltages
into digital value (not so in D/A)
 Two converters are NOT inverses
 Transmission parameters affect multi-tone tests
 Gain, signal-to-distortion ratio, intermodulation
distortion, noise power ratio, differential phase
shift, envelop delay distortion
 Intrinsic parameters – Converter specifications
 Full scale range (FSR), gain, # bits, static
linearity (differential and integral), maximum
clock rate, code format, settling time (D/A),
glitch area (D/A)

Ideal Transfer Functions
A/D Converter D/A Converter

Offset Error

Gain Error

D/A Transfer Function
Non-Linearity Error

Flash A/D Converter

Differential Linearity Error
 Differential linearity function – How each code

step differs from ideal or average step (by code
number), as fraction of LSB
 Subtract average count for each code tally,
express that in units of LSBs
 Repeat test waveform 100 to 150 times, use
slow triangle wave to increase resolution

Linear Histogram and
DLE of 8-bit ADC
© 1987 IEEE

D/A Differential Test
Fixture
© 1987 IEEE
Measure Vy – Vx difference, not absolute Vx or Vy

Summary
 DSP-based tester has:
 Waveform Generator
 Waveform Digitizer
 High frequency clock with dividers for
synchronization
 A/D and D/A Test Parameters
 Transmission
 Intrinsic
 A/D and D/A Faults: offset, gain, non-linearity
errors
 Measured by DLE, ILE, DNL, and INL
 A/D Test Histograms – static linear and sinusoidal
 D/A Test –- Differential Test Fixture

DSP-Based Testing
 Quantization Error – Introduced into
measured signal by discrete sampling
 Quantum Voltage – Corresponds to flip of
LSB of converter
 Single-Tone Test -- Test of DUT using only
one sinusoidal tone
 Tone – Pure sinusoid of f, A, and phase f
 Transmission (Performance) Parameter --
indicates how channel with embedded
analog circuit affects multi-tone test signal
 UTP – Unit test period: joint sampling
period for analog stimulus and response
Coherent Measurement
Method
 Unit Test Period is integration interval P
 Has integral # of stimulus periods M
 Has integral # of DUT output periods N
 Stimulus & sampling are phase locked
 To obtain maximum information from
sampling, M and N are relatively prime
 Ft – tone frequency
 Fs – sampling rate

CODEC Testing Example
 Serial ADC in digital telephone exchange
 Sampling rate 8000 s/s
 Audio frequency range 300 – 3400 Hz
Ft = 1000 Hz Fs = 8000 s/s
P = 50 msec
M = 50 cycles N = 400 samples
 Problem: M and N not relatively prime
 All samples fall on waveform at certain
phases – sample only 8/255 CODEC steps

CODEC Testing Solution
 Set Fs = 400 ks/s – impossibly fast
 Better – Adjust Ft slightly, signal sampled
at different points
 Necessary relationships:
Ft = M x D Fs = N x D
D = 1 / UTP
Ft M
=
Fs N

Good CODEC Parameters
Ft = 1020 Hz Fs = 8000 s/s

P = UTP = 50 msec D = 20 Hz
M = 51 cycles N = 400 samples
 M and N now relatively prime
 All samples fall on waveform at different
phases – samples all CODEC steps

Unit Test Period
© 1987 IEEE

Spectral Test of A/D
Converter
© 1987 IEEE

Bad A/D Converter Test
© 1987 IEEE

Good A/D Converter Test
© 1987 IEEE

Spectral DSP-Based Testing
Components
© 1987 IEEE

Correlation Model
© 1987 IEEE
 Cross-correlation – compare 2 different signals
 Autocorrelation – compare 1 signal with itself

Fourier Voltmeter
1 Principle
st
© 1987 IEEE
For signals A and B, if P is infinite, R = 0. If P
is finite and contains integer # cycles of both
A and B, then cross-correlation R = 0,
regardless of phase or amplitude

Fourier Voltmeter
2 Principle
nd
© 1987 IEEE
If signals A and B of same f are 90o out of
phase, and P contains an integer J # of
signal cycles, then cross-correlation R = 0,
regardless of amplitude or starting point

Conceptual Discrete Fourier
Voltmeter
© 1987 IEEE

A/D Converter Spectrum
© 1987 IEEE
Audio source at 1076 Hz sampled at 44.1 kHz

Coherent Multi-Tone
Testing
© 1987 IEEE

Single-Tone Test Example
© 1987 IEEE

Multi-Tone Test Example
© 1987 IEEE

Total Harmonic Distortion
(THD)
 Measures energy appearing in harmonics
(H2, H3, …) of fundamental tone H1 as % of
energy in the fundamental frequency in
response spectrum
H2 H3 H1
10 10
10 + 10 + … + 10 0
 THD = 10
H1
20
10

DSP Testing Summary
 Analog testing greatly increasing in
importance
 System-on-a-chip
 Wireless
 Personal computer multi-media
 Automotive electronics
 Medicine
 Internet telephony
 CD players and audio electronics
 Analog testing NOT deterministic like digital
 Statistical testing process, electrical noise

Delay Test

Delay Test Definition
 A circuit that passes delay test must
produce correct outputs when inputs are
applied and outputs observed with
specified timing.
 For a combinational or synchronous
sequential circuit, delay test verifies the
limits of delay in combinational logic.
 Delay test problem for asynchronous
circuits is complex and not well
understood.

Digital Circuit Timing
Input Output Transient
Signal region
Observation
changes instant
Inputs
Comb.
logic
Synchronized Outputs
With clock
time
Clock period
Circuit Delays
 Switching or inertial delay is the interval between
input change and output change of a gate:
 Depends on input capacitance, device (transistor)
characteristics and output capacitance of gate.
 Also depends on input rise or fall times and states of
other inputs (second-order effects).
 Approximation: fixed rise and fall delays (or min-max
delay range, or single fixed delay) for gate output.
 Propagation or interconnect delay is the time a
transition takes to travel between gates:
 Depends on transmission line effects (distributed R, L,
C parameters, length and loading) of routing paths.
 Approximation: modeled as lumped delays for gate
inputs.
 See Section 5.3.5 for timing models.

Event Propagation Delays
Single lumped inertial delay modeled for each gate
PI transitions assumed to occur without time skew
Path P1
13
0 1
246
P2 1
0 2 3
P3
0 2 5

Robust Test
 A robust test guarantees the detection of a
delay fault of the target path, irrespective
of delay faults on other paths.
 A robust test is a combinational vector-pair,
V1, V2, that satisfies following conditions:
 Produce real events (different steady-state
values for V1 and V2) on all on-path signals.
 All on-path signals must have controlling
events arriving via the target path.
 A robust test is also a non-robust test.
 Concept of robust test is general – robust
tests for other fault models can be defined.
A Five-Valued Algebra
 Signal States: S0, U0 (F0), S1, U1 (R1), XX.
 On-path signals: F0 and R1.
 Off-path signals: F0=U0 and R1=U1.
Input 1 Input 1
AND S0 U0 S1 U1 XX OR S0 U0 S1 U1 XX
S0 S0 S0 S0 S0 S0 S0 S0 U0 S1 U1 XX
U0 S0 U0 U0 U0 U0 U0 U0 U0 S1 U1 XX
Input 2
Input 2
S1 S0 U0 S1 U1 XX S1 S1 S1 S1 S1 S1
U1 S0 U0 U1 U1 XX U1 U1 U1 S1 U1 U1
XX S0 U0 XX XX XX XX XX XX S1 U1 XX
Input
S0 U0 S1 U1 XX Ref.:
NOT
Lin-Reddy
S1 U1 S0 U0 XX IEEETCAD-87
Non-Robust Test Generation
Fault P2 – rising transition through path P2 has no robust test.
C. Set input of AND gate to

propagate R1 to output
D. R1 propagates through
XX U1 OR gate since off-path
R1 input is U0
R1
Path P2 R1
A. Place R1 at
path origin
R1
R1 U1 U0 Non-robust test requires
XX Static sensitization:
S0=U0, S1=U1
U0
B. Propagate R1 through OR gate;
interpreted as U1 on off-path signal; Non-robust test:
propagates as U0 through NOT gate U1, R1, U0

Path-Delay Faults (PDF)
 Two PDFs (rising and falling transitions) for each physical
path.
 Total number of paths is an exponential function of gates.
Critical paths, identified by static timing analysis (e.g.,
Primetime from Synopsys), must be tested.
 PDF tests are delay-independent. Robust tests are
preferred, but some paths have only non-robust tests.
 Three types of PDFs (Gharaybeh, et al., JETTA (11), 1997):
 Singly-testable PDF – has a non-robust or robust test.
 Multiply-testable PDF – a set of singly untestable faults
that has a non-robust or robust test. Also known as
functionally testable PDF.
 Untestable PDF – a PDF that is neither singly nor multiply
testable.
 A singly-testable PDF has at least one single-input change
(SIC) non-robust test.

Slow-Clock Test
Input Combinational Output
latches circuit latches
Input Output
test clock Test Rated test clock
clock clock
period period
Input
test clock
Output
test clock
V1 V2
applied applied Output
latched
Normal-Scan Test
V2 states generated, (A) by one-bit scan shift of V1, or
(B) by V1 applied in functional mode. Result
latched
V1 PIs V2 PIs
PI Combinational PO applied applied
Scanin Gen. V2 Path Result
circuit tested
V1 states states scanout
SCAN- CK TC t
OUT Slow clock Rated
SFF CK period
TC
Normal
mode
Scan mode Scan mode
SFF (A)
SCANIN
Slow CK
CK TC period
TC
CK: system clock (B) Scan mode Normal mode Scan mode
TC: test control
SFF: scan flip-flop

Variable-Clock Sequential
Test Off-path
flip-flop
PI PI PI PI PI PI
0 1
T 1 T n-2 1 T n-1 1 T n 1 T n+1 T n+m
2 2 2
0 D
PO PO PO PO PO PO
Path Fault effect
Initialization sequence activation propagation
(slow clock) (rated sequence
Clock) (slow clock)
Note: Slow-clock makes the circuit fault-free in the presence of
delay faults.

At-Speed Test
 At-speed test means application of test vectors at
the rated-clock speed.
 Two methods of at-speed test.
 External test:
 Vectors may test one or more functional critical
(longest delay) paths and a large percentage
(~100%) of transition faults.
 High-speed testers are expensive.
 Built-in self-test (BIST):
 Hardware-generated random vectors applied to
combinational or sequential logic.
 Only clock is externally supplied.
 Non-functional paths that are longer than the
functional critical path can be activated and cause
a good circuit to fail.
 Some circuits have initialization problem.

Timing Design & Delay Test
 Timing simulation:
 Critical paths are identified by static (vector-less)
timing analysis tools like Primetime (Synopsys).
 Timing or circuit-level simulation using designer-
generated functional vectors verifies the design.
 Layout optimization: Critical path data are
used in placement and routing. Delay
parameter extraction, timing simulation and
layout are repeated for iterative improvement.
 Testing: Some form of at-speed test is
necessary. PDFs for critical paths and all
transition faults are tested.

Summary
 Path-delay fault (PDF) models distributed delay
defects. It verifies the timing performance of a
manufactured circuit.
 Transition fault models spot delay defects and is
testable by modified stuck-at fault tests.
 Variable-clock method can test delay faults but the
test time can be long.
 Critical paths of non-scan sequential circuits can be
effectively tested by rated-clock tests.
 Delay test methods (including BIST) for non-scan
sequential circuits using slow ATE require
investigation:
 Suppression of non-functional path activation in BIST.
 Difficulty of rated-clock PDF test generation.
 Long sequences of variable-clock tests.

IDDQ Test

Basic Principle of IDDQ
Testing
 Measure IDDQ current through Vss bus

Capacitive Coupling of
Floating Gates
 Cpb – capacitance from
poly to bulk
 Cmp – overlapped metal
wire to poly
 Floating gate voltage
depends on capacitances
and node voltages
 If nFET and pFET get
enough gate voltage to
turn them on, then IDDQ
test detects this defect
 K is the transistor gain
Bridging Faults S1 – S5
 Caused by absolute short
(< 50 W) or higher R
 Segura et al. evaluated
testing of bridges with 3
CMOS inverter chain
 IDDQRb tests fault when
Rb > 50 KW or
0  Rb  100 KW
 Largest deviation when
Vin = 5 V bridged nodes at
opposite logic values
Delay Faults
 Most random CMOS defects cause a timing

delay fault, not catastrophic failure
 Many delay faults detected by IDDQ test –
late switching of logic gates keeps IDDQ
elevated
 Delay faults not detected by IDDQ test
 Resistive via fault in interconnect
 Increased transistor threshold voltage
fault

Leakage Faults
 Gate oxide shorts cause leaks between gate &

source or gate & drain
 Mao and Gulati leakage fault model:
 Leakage path flags: fGS, fGD, fSD, fBS, fBD, fBG
G = gate, S = source, D = drain, B = bulk
 Assume that short does not change logic values

Weak Faults
 nFET passes logic 1 as 5 V – Vtn

 pFET passes logic 0 as 0 V + |Vtp|
 Weak fault – one device in C-switch does not
turn on
 Causes logic value degradation in C-switch

Gate Oxide Short

Quietest Results
Ckt. # of # of % Leakage
Tran- Leakage Selected Fault
Sistors Faults Vectors Coverage
1 7584 39295 0.5 % 94.84 %
2 42373 220571 0.99 % 90.50 %
Ckt. # of % Weak
Weak Selected Fault
Faults Vectors Coverage
1 1923 0.35 % 85.3 %
2 1497 0.21 % 87.64 %
Sematech Results
 Test process: Wafer Test Package Test
Burn-In & Retest Characterize & Failure
Analysis
 Data for devices failing some, but not all, tests.
Scan-based Stuck-at
IDDQ (5 mA limit)
Scan-based delay
pass pass fail fail
pass 6 1463 7 pass
fail 14 0 34 1 pass
pass 6 1 13 8 fail
fail 52 36 1251 fail
pass fail pass fail
Functional
Summary
 IDDQ tests improve reliability, find defects
causing:
 Delay, bridging, weak faults
 Chips damaged by electro-static discharge
 No natural breakpoint for current threshold
 Get continuous distribution – bimodal
would be better
 Conclusion: now need stuck-fault, IDDQ, and
delay fault testing combined
 Still uncertain whether IDDQ tests will remain
useful as chip feature sizes shrink further

Part III
DESIGN FOR
TESTABILITY
Scan Design

Definition
 Design for testability (DFT) refers to those design
techniques that make test generation and test
application cost-effective.
 DFT methods for digital circuits:
 Ad-hoc methods
 Structured methods:
 Scan
 Partial Scan
 Built-in self-test (BIST)
 Boundary scan
 DFT method for mixed-signal circuits:
 Analog test bus

Ad-Hoc DFT Methods
 Good design practices learnt through experience are
used as guidelines:
 Avoid asynchronous (unclocked) feedback.
 Make flip-flops initializable.
 Avoid redundant gates. Avoid large fanin gates.
 Provide test control for difficult-to-control signals.
 Avoid gated clocks.
 ...
 Consider ATE requirements (tristates, etc.)
 Design reviews conducted by experts or design auditing
tools.
 Disadvantages of ad-hoc DFT methods:
 Experts and tools not always available.
 Test generation is often manual with no guarantee of
high fault coverage.
 Design iterations may be necessary.

Scan Design
 Circuit is designed using pre-specified design
rules.
 Test structure (hardware) is added to the
verified design:
 Add a test control (TC) primary input.
 Replace flip-flops by scan flip-flops (SFF) and connect
to form one or more shift registers in the test mode.
 Make input/output of each scan shift register
controllable/observable from PI/PO.
 Use combinational ATPG to obtain tests for all
testable faults in the combinational logic.
 Add shift register tests and convert ATPG tests
into scan sequences for use in manufacturing
test.
Scan Design Rules
 Use only clocked D-type of flip-flops for all

state variables.
 At least one PI pin must be available for test;
more pins, if available, can be used.
 All clocks must be controlled from PIs.
 Clocks must not feed data inputs of flip-flops.

Scan Flip-Flop (SFF)
D Master latch Slave latch
TC
Logic Q
overhead
MUX
SD Q
CK D flip-flop
CK Master open Slave open

t
TC Normal mode, D selected Scan mode, SD selected

t

Level-Sensitive Scan-Design
Flip-Flop (LSSD-SFF)
Master latch Slave latch
D
Q
MCK Q
SCK D flip-flop
SD
MCK
Normal
mode
Logic TCK
overhead
TCK MCK
mode
Scan
TCK
SCK t
Adding Scan Structure
PI PO
Combinational SFF SCANOUT
logic SFF
SFF
TC or TCK Not shown: CK or

MCK/SCK feed all
SCANIN SFFs.
Comb. Test Vectors
PI I1 I2 O1 O2 PO
Combinational
SCANIN
SCANOUT
TC
logic
Next
Presen S1 S2 N1 N2 state
t
state

Comb. Test Vectors
Don’t care
or random
PI I1 I2 bits
SCANIN S1 S2
TC 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0000000
PO O1 O2
SCANOUT N1 N2
Sequence length = (ncomb + 1) nsff + ncomb clock periods

ncomb = number of combinational vectors
nsff = number of scan flip-flops
Testing Scan Register
 Scan register must be tested prior to
application of scan test sequences.
 A shift sequence 00110011 . . . of length
nsff+4 in scan mode (TC=0) produces 00, 01,
11 and 10 transitions in all flip-flops and
observes the result at SCANOUT output.
 Total scan test length: (ncomb
+ 2) nsff + ncomb + 4 clock periods.
 Example: 2,000 scan flip-flops, 500 comb.
vectors, total scan test length ~ 106 clocks.
 Multiple scan registers reduce test length.

Scan Overheads
 IO pins: One pin necessary.
 Area overhead:
 Gate overhead = [4 nsff/(ng+10nff)] x 100%,
where ng = comb. gates; nff = flip-flops;
Example – ng = 100k gates, nff = 2k flip-flops,
overhead = 6.7%.
 More accurate estimate must consider scan
wiring and layout area.
 Performance overhead:
 Multiplexer delay added in combinational
path; approx. two gate-delays.
 Flip-flop output loading due to one additional
fanout; approx. 5-6%.
ATPG Example: S5378
Original Full-scan
Number of combinational gates 2,781 2,781

Number of non-scan flip-flops (10 gates each) 179 0
Number of scan flip-flops (14 gates each) 0 179
Gate overhead 0.0% 15.66%
Number of faults 4,603 4,603
PI/PO for ATPG 35/49 214/228
Fault coverage 70.0% 99.1%
Fault efficiency 70.9% 100.0%
CPU time on SUN Ultra II, 200MHz processor 5,533 s 5s
Number of ATPG vectors 414 585
Scan sequence length 414 105,662

Summary
 Scan is the most popular DFT technique:
 Rule-based design
 Automated DFT hardware insertion
 Combinational ATPG
 Advantages:
 Design automation
 High fault coverage; helpful in diagnosis
 Hierarchical – scan-testable modules are easily
combined into large scan-testable systems
 Moderate area (~10%) and speed (~5%) overheads
 Disadvantages:
 Large test data volume and long test time
 Basically a slow speed (DC) test

Built-In Self-Testing
(BIST)

Economics – BIST Costs
 Chip area overhead for:
 Testcontroller
 Hardware pattern generator
 Hardware response compacter
 Testing of BIST hardware
 Pin overhead -- At least 1 pin needed to
activate BIST operation
 Performance overhead – extra path delays due
to BIST
 Yield loss – due to increased chip area or more
chips In system because of BIST
 Reliability reduction – due to increased area
 Increased BIST hardware complexity –
happens when BIST hardware is made testable
BIST Benefits
 Faults tested:
 Single combinational / sequential stuck-at
faults
 Delay faults
 Single stuck-at faults in BIST hardware
 BIST benefits
 Reduced testing and maintenance cost
 Lower test generation cost
 Reduced storage / maintenance of test patterns
 Simpler and less expensive ATE
 Can test many units in parallel
 Shorter test application times
 Can test at functional system speed
BIST Process
 Test controller – Hardware that activates self-

test simultaneously on all PCBs
 Each board controller activates parallel chip BIST
Diagnosis effective only if very high fault
coverage
BIST Architecture
 Note: BIST cannot test wires and transistors:

 From PI pins to Input MUX
 From POs to output pins
Example External XOR
LFSR
 Characteristic polynomial f (x) = 1 + x + x3

(read taps from right to left)
External XOR LFSR
 Pattern sequence for example LFSR (earlier):
X0 1 0 0 1 0 1 1 1 0
X1 0 0 1 0 1 1 1 0 0 …
X2 0 1 0 1 1 1 0 0 1
 Always have 1 and xn terms in polynomial

 Never repeat an LFSR pattern more than 1 time –
Repeats same error vector, cancels fault effect
X0 (t + 1) 0 1 0 X 0 (t)
X1 (t + 1) = 0 0 1 X 1 (t)
X2 (t + 1) 1 1 0 X 2 (t)
Response Compaction
 Severe amounts of data in CUT response to

LFSR patterns – example:
 Generate 5 million random patterns
 CUT has 200 outputs
 Leads to: 5 million x 200 = 1 billion bits
response
 Uneconomical to store and check all of these
responses on chip
 Responses must be compacted

Definitions
 Aliasing – Due to information loss, signatures
of good and some bad machines match
 Compaction – Drastically reduce # bits in
original circuit response – lose information
 Compression – Reduce # bits in original
circuit response – no information loss – fully
invertible (can get back original response)
 Signature analysis – Compact good machine
response into good machine signature.
Actual signature generated during testing,
and compared with good machine signature
 Transition Count Response Compaction –
Count # transitions from 0 1 and 1 0 as
a signature
LFSR for Response
Compaction
 Use cyclic redundancy check code (CRCC)
generator (LFSR) for response compacter
 Treat data bits from circuit POs to be compacted
as a decreasing order coefficient polynomial
 CRCC divides the PO polynomial by its
characteristic polynomial
 Leaves remainder of division in LFSR
 Must initialize LFSR to seed value (usually 0)
before testing
 After testing – compare signature in LFSR to
known good machine signature
 Critical: Must compute good machine signature
Example Modular LFSR
Response Compacter
 LFSR seed value is “00000”

Polynomial Division
Inputs X0 X1 X2 X3 X4
Initial State 0 0 0 0 0
1 1 0 0 0 0
0 0 1 0 0 0
Logic 0 0 0 1 0 0
Simulation: 0 0 0 0 1 0
1 1 0 0 0 1
0 1 0 0 1 0
1 1 1 0 0 1
0 1 0 1 1 0
Logic simulation: Remainder = 1 + x2 + x3
0 1 0 1 0 0 0 1
0 . x0 + 1 . x1 + 0 . x2 + 1 . x3 + 0 . x4 + 0 . x5 + 0 . x6
+ 1 . x7
Symbolic Polynomial
Division
x2 + 1
x5 + x3 + x + 1 x7 + x3 +x
x7 + x5 + x3 + x2
x5 + x2 + x
x5 + x3 +x +1
remainder x3 + x2 +1
Remainder matches that from logic simulation

of the response compacter!

Multiple-Input Signature
Register (MISR)
 Problem with ordinary LFSR response
compacter:
 Too much hardware if one of these is put on
each primary output (PO)
 Solution: MISR – compacts all outputs into one
LFSR
 Works because LFSR is linear – obeys
superposition principle
 Superimpose all responses in one LFSR –
final remainder is XOR sum of remainders of
polynomial divisions of each PO by the
characteristic polynomial
Modular MISR Example
X0 (t + 1) 0 0 1 X 0 (t) d0 (t)
X1 (t + 1) = 1 0 1 X 1 (t) + d1 (t)
X2 (t + 1) 0 1 0 X 2 (t) d2 (t)

Aliasing Theorems
 Theorem 15.1: Assuming that each circuit PO dij
has probability p of being in error, and that all
outputs dij are independent, in a k-bit MISR,
Pal = 1/(2k), regardless of initial condition of
MISR. Not exactly true – true in practice.
 Theorem 15.2: Assuming that each PO dij has
probability pj of being in error, where the pj
probabilities are independent, and that all
outputs dij are independent, in a k-bit MISR,
Pal = 1/(2k), regardless of the initial condition.
Built-in Logic Block
Observer (BILBO)
 Combined functionality of D flip-flop, pattern
generator, response compacter, & scan chain
 Reset all FFs to 0 by scanning in zeros

Example BILBO Usage
 SI – Scan In
 SO – Scan Out
 Characteristic polynomial: 1 + x + … + xn
 CUTs A and C: BILBO1 is MISR, BILBO2 is LFSR
 CUT B: BILBO1 is LFSR, BILBO2 is MISR

Circuit Initialization
 Full-scan BIST – shift in scan chain seed before starting
BIST
 Partial-scan BIST – critical to initialize all FFs before
BIST starts
 Otherwise we clock X’s into MISR and signature is
not unique and not repeatable
 Discover initialization problems by:
1. Modeling all BIST hardware
2. Setting all FFs to X’s
3. Running logic simulation of CUT with BIST hardware

Circuit Initialization
(continued)
 If MISR finishes with BIST cycle with X’s in
signature, Design-for-Testability initialization
hardware must be added
 Add MS (master set) or MR (master reset)
lines on flip-flops and excite them before
BIST starts
 Otherwise:
1. Break all cycles of FF’s
2. Apply a partial BIST synchronizing
sequence to initialize all FF’s
3. Turn on the MISR to compact the response
Test Point Insertion
 BIST does not detect all faults:

 Test patterns not rich enough to test all
faults
 Modify circuit after synthesis to improve
signal controllability
 Observability addition – Route internal signal
to extra FF in MISR or XOR into existing FF in
MISR

SRAM BIST with MISR
 Use MISR to compress memory outputs
 Control aliasing by repeating test:
 With different MISR feedback polynomial
 With RAM test patterns in reverse order
 March test:
{ (w Address); (r Address); (w Address);
(r Address); (r Address); (w Address);
(r Address); (r Address) }
 Not proven to detect coupling or address
decoder faults

BIST System with MISR

Summary
 LFSR pattern generator and MISR response
compacter – preferred BIST methods
 BIST has overheads: test controller, extra
circuit delay, Input MUX, pattern generator,
response compacter, DFT to initialize circuit &
test the test hardware
 BIST benefits:
 At-speed testing for delay & stuck-at faults
 Drastic ATE cost reduction
 Field test capability
 Faster diagnosis during system test
 Less effort to design testing process
 Shorter test application times

IEEE 1149.1
Boundary Scan Standard

Motivation for Standard
 Bed-of-nails printed circuit board tester gone
 We put components on both sides of PCB &
replaced DIPs with flat packs to reduce
inductance
 Nails would hit components
 Reduced spacing between PCB wires
 Nails would short the wires
 PCB Tester must be replaced with built-in test
delivery system -- JTAG does that
 Need standard System Test Port and Bus
 Integrate components from different vendors
 Test bus identical for various components
 One chip has test hardware for other chips
Purpose of Standard
 Lets test instructions and test data be serially
fed into a component-under-test (CUT)
 Allows reading out of test results
 Allows RUNBIST command as an instruction
 Too many shifts to shift in external tests
 JTAG can operate at chip, PCB, & system levels
 Allows control of tri-state signals during testing
 Lets other chips collect responses from CUT
 Lets system interconnect be tested separately
from components
 Lets components be tested separately from
wires
System Test Logic

Instruction Register
Loading with JTAG

System View of Interconnect

Boundary Scan Chain View

Elementary Boundary
Scan Cell

Serial Board / MCM Scan

Parallel Board / MCM Scan

Tap Controller Signals
 Test Access Port (TAP) includes these signals:
 Test Clock Input (TCK) -- Clock for test logic
Can run at different rate from system clock
 Test Mode Select (TMS) -- Switches system
from functional to test mode
 Test Data Input (TDI) -- Accepts serial test
data and instructions -- used to shift in
vectors or one of many test instructions
 Test Data Output (TDO) -- Serially shifts out
test results captured in boundary scan chain
(or device ID or other internal registers)
 Test Reset (TRST) -- Optional asynchronous
TAP controller reset
SAMPLE / PRELOAD
Instruction -- SAMPLE
Purpose:
1. Get snapshot of normal chip output signals
2. Put data on bound. scan chain before next instr.

SAMPLE / PRELOAD
Instruction -- PRELOAD

EXTEST Instruction
 Purpose: Test off-chip circuits and board-
level interconnections

INTEST Instruction
 Purpose:
1. Shifts external test patterns onto component
2. External tester shifts component responses out

RUNBIST Instruction
 Purpose: Allows you to issue BIST command to
component through JTAG hardware
 Optional instruction
 Lets test logic control state of output pins
1. Can be determined by pin boundary scan cell
2. Can be forced into high impedance state
 BIST result (success or failure) can be left in
boundary scan cell or internal cell
 Shift out through boundary scan chain
 May leave chip pins in an indeterminate state
(reset required before normal operation
resumes)
CLAMP Instruction
 Purpose: Forces component output signals
to be driven by boundary-scan register
 Bypasses the boundary scan chain by
using the one-bit Bypass Register
 May have to add RESET hardware to
control on-chip logic so that it does not
get damaged (by shorting 0’s and 1’s onto
an internal bus, etc.)

IDCODE Instruction
 Purpose: Connects the component device

identification register serially between TDI
and TDO
 In the Shift-DR TAP controller state
 Allows board-level test controller or
external tester to read out component ID
 Required whenever a JEDEC identification
register is included in the design

Device ID Register --
JEDEC Code
MSB LSB
31 28 27 12 11 1 0
Version Part Manufacturer ‘1’
Number Identity
(4 bits) (16 bits) (11 bits) (1 bit)

USERCODE Instruction
 Purpose: Intended for user-programmable
components (FPGA’s, EEPROMs, etc.)
 Allows external tester to determine user
programming of component
 Selects the device identification register as
serially connected between TDI and TDO
 User-programmable ID code loaded into device
identification register
 On rising TCK edge
 Switches component test hardware to its
system function
 Required when Device ID register included on
user-programmable component
HIGHZ Instruction
 Purpose: Puts all component output pin signals
into high-impedance state
 Control chip logic to avoid damage in this mode
 May have to reset component after HIGHZ runs

BYPASS Instruction
 Purpose: Bypasses scan chain with 1-bit register

Summary
 Boundary Scan Standard has become
absolutely essential --
 No longer possible to test printed circuit
boards with bed-of-nails tester
 Not possible to test multi-chip modules
at all without it
 Supports BIST, external testing with
Automatic Test Equipment, and
boundary scan chain reconfiguration as
BIST pattern generator and response
compacter
 Now getting widespread usage
IEEE 1149.4 Analog Test
Bus

Analog Test Bus
 PROs:
 Usable with digital JTAG boundary scan
 Adds analog testability – both controllability
and observability
 Eliminates large area needed for analog test
points
 CONs:
 May have a 5 % measurement error
 C-switch sampling devices couple all probe
points capacitively, even with test bus off –
requires more elaborate (larger) switches
 Stringent limit on how far data can move
through the bus before it must be digitized to
retain accuracy
Analog Test Bus Diagram

Analog Boundary Module

Chaining of 1149.4 ICs

System Test

A System and Its Testing
 A system is an organization of components
(hardware/software parts and subsystems) with
capability to perform useful functions.
 Functional test verifies integrity of system:
 Checks for presence and sanity of subsystems
 Checks for system specifications
 Executes selected (critical) functions
 Diagnostic test isolates faulty part:
 For field maintenance isolates lowest replaceable
unit (LRU), e.g., a board, disc drive, or I/O subsystem
 For shop repair isolates shop replaceable unit (SRU),
e.g., a faulty chip on a board
 Diagnostic resolution is the number of suspected
faulty units identified by test; fewer suspects mean
higher resolution

Functional Test
 All or selected (critical) operations executed
with non-exhaustive data.
 Tests are a subset of design verification
tests (test-benches).
 Software test metrics used: statement,
branch and path coverages; provide low
(~70%) structural hardware fault coverage.
 Examples:
 Microprocessor test – all instructions with
random data (David, 1998).
 Instruction-set fault model – wrong instruction is
executed (Thatte and Abraham, IEEETC-1980).

Gate-Level Diagnosis
Karnaugh map
Logic circuit (shaded squares are true outputs)
b
a d T2 T1
b e
c a T3 T4
c
Stuck-at fault tests:
T1 = 010
T2 = 011
T3 = 100
T4 = 110

Gate Replacement Fault
Faulty circuit Karnaugh map
(OR replaced by AND) (faulty output shown in red)
b
a d T2 T1
b e
c a T3 T4
c
Stuck-at fault tests:
T1 = 010 (pass)
T2 = 011 (fail)
T3 = 100 (pass)
T4 = 110 (fail)

Fault Dictionary
Fault Test syndrome
t1 t2 t3 t4
No fault 0 0 0 0
a0, b0, d0 0 0 0 1 a0 : Line a stuck-

at-0
a1 1 0 0 0
ti = 0, if Ti passes
b1 0 0 1 0 = 1, if Ti fails
c0 0 1 0 0
c1, d1, e1 1 0 1 0
e0 0 1 0 1
Diagnosis with Dictionary
Dictionary look-up with minimum Hamming distance
Fault Test syndrome Diagnosis

t1 t2 t3 t4
OR AND 0 1 0 1 e0
OR-bridge (a,c) 0 0 1 0 b1
OR NOR 1 1 1 1 c1, d1, e1, e0

System Test:
Partitioning for Test
 Partition according to test methodology:
 Logic blocks
 Memory blocks
 Analog blocks
 Provide test access:
 Boundary scan
 Analog test bus
 Provide test-wrappers (also called collars)
for cores.

Test-Wrapper for a Core
 Test-wrapper (or collar) is the logic added around a core
to provide test access to the embedded core.
 Test-wrapper provides:
 For each core input terminal
 A normal mode – Core terminal driven by host chip
 An external test mode – Wrapper element observes core
input terminal for interconnect test
 An internal test mode – Wrapper element controls state
of core input terminal for testing the logic inside core
 For each core output terminal
 A normal mode – Host chip driven by core terminal
 An external test mode – Host chip is driven by wrapper
element for interconnect test
 An internal test mode – Wrapper element observes core
outputs for core test

A Test-Wrapper
Wrapper
elements
core outputs
core inputs
Functional
Functional
Scan chain
Scan chain Core
from/to
External
Test pins Scan chain Wrapper
test
controlle
to/from TAP r
Overhead Estimate
Rent’s rule: For a logic block the number of gates G
and the number of terminals t are related by
t = K Ga
where 1 < K < 5, and a ~ 0.5.
Assume that block area A is proportional to G, i.e.,

t is proportional to A 0.5. Since test logic is added
to each terminal t,
Test logic added to terminals

Overhead = ------------------------------------------------- ~ A –0.5
A

DFT Architecture for SOC
Test Test
User defined test access mechanism (TAM)
source sink
Func.
outputs Functional
Functional Func. outputs
inputs
wrapper
wrapper
Module inputs Module
Test
Test
1 N
Instruction register control
Test access port (TAP)

Serial instruction data TRST
TDI
TMS
TCK
TDO
SOC inputs SOC outputs

Summary
 Functional test: verify system hardware, software,
function and performance; pass/fail test with
limited diagnosis; high (~100%) software coverage
metrics; low (~70%) structural fault coverage.
 Diagnostic test: High structural coverage; high
diagnostic resolution; procedures use fault
dictionary or diagnostic tree.
 SOC design for testability:
 Partition SOC into blocks of logic, memory and
analog circuitry, often on architectural boundaries.
 Provide external or built-in tests for blocks.
 Provide test access via boundary scan and/or
analog test bus.
 Develop interconnect tests and system functional
tests.
 Develop diagnostic procedures.

References
 M.L. Bushnell and V. D. Agrawal, Essentials
of Electronic Testing for Digital, Memory
and Mixed-Signal VLSI Circuits, Boston:
Kluwer Academic Publishers, 2000, ISBN
0-7923-7991-8.
 For a course taught by the authors at
Rutgers University, see website:
http://cm.bell-labs.com/cm/cs/who/va

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Essentials of

Essentials of Test: Agrawal & Bushnell 1

Essentials of Test: Agrawal & Bushnell 2

Design synthesis and Verification

Essentials of Test: Agrawal & Bushnell 4

October 28, 2001 Essentials of Test: Agrawal & Bushnell 5

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1997 -2001 2003 - 2006

Feature size (micron) 0.25 - 0.15 0.13 - 0.10

* SIA Roadmap, IEEE Spectrum, July 1999

October 28, 2001 Essentials of Test: Agrawal & Bushnell 7

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 Determines whether manufactured chip

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 Parametric – measures electrical

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 ATE and Manufacturing World – any vectors

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Cost of fabricating and testing a wafer

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Measured chip fallout

Y (T ) for Af = 2.1 and b = 0.083

Stuck-at fault coverage, T

Stuck-at fault coverage (%)

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 I/O function tests inadequate for

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Ref.: M. J. Howes and D. V. Morgan, Reliability and Degradation -

Ref.: J. Bateson, In-Circuit Testing, Van Nostrand Reinhold, 1985.

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sa0 sa1 sa0 sa1

sa0 sa1 sa0 sa1

sa0 sa1 sa0 sa1

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s-a-1 Only test of F1

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Response Design Design

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