Teknik Antarmuka dan Periferal

Sesi 3
TEI302
 I/O Bus and Interface
I/O bus
Data
Processor Address
Control

Interface Interface Interface Interface

Keyboard
and Printer Magnetic Magnetic
display disk tape
terminal

Each peripheral has an interface module associated with it

Interface
• Decodes the device address (device code)
• Decodes the commands (operation)
• Provides signals for the peripheral controller
• Synchronizes the data flow and supervises the transfer rate between
peripheral and CPU or Memory
Typical I/O instruction
Op. code Device address Function code
(Command)
 I/O Bus Connection
Connection of I/O Bus to CPU
Op. Device Function Accumulator Computer
code address code register I/O
control CPU

Sense lines
Data lines
I/O
Function code lines
bus
Device address lines

Connection of I/O Bus to One Interface

Data lines
Peripheral
register

Device Buffer register

Output
address peripheral
I/O AD = 1101 Interface
device
and
bus Logic controller

Function code Command

decoder

Sense lines Status

register
 I/O Bus and Memory Bus
Functions of Buses
• Memory Bus for information transfers between CPU and the Main Memory
• I/O Bus for information transfers between CPU and I/O devices through their I/O
interface
• Many computers use a common single bus system for both memory and I/O
interface units
- Use one common bus but separate control lines for each function
- Use one common bus with common control lines for both functions
• Some computer systems use two separate buses, one to communicate with memory
and the other with I/O interfaces
• Communication between CPU and all interface units is via a common I/O Bus
• An interface connected to a peripheral device may have a number of data
registers , a control register, and a status register
• A command is passed to the peripheral by sending to the appropriate interface
register
• Function code and sense lines are not needed (Transfer of data, control, and
status information is always via the common I/O Bus)
 Isolated vs Memory Mapped I/O
Isolated I/O
• Separate I/O read/write control lines in addition to memory read/write
control lines
• Separate (isolated) memory and I/O address spaces
• Distinct input and output instructions

Memory-mapped I/O
• A single set of read/write control lines
(no distinction between memory and I/O transfer)
• Memory and I/O addresses share the common address space
-> reduces memory address range available
• No specific input or output instruction
-> The same memory reference instructions can be used for I/O transfers
• Considerable flexibility in handling I/O operations
 I/O Interface
Port A I/O data

Bidirectional register
Bus
data bus buffers
Port B I/O data
register
Chip select I/O
CPU CS
Register select
Control Control Device
RS1 Timing
Register select register
RS0 and
I/O read Control
RD Status Status
I/O write
WR register

CS RS1 RS0 Register selected

0 x x None - data bus in high-impedence
1 0 0 Port A register
1 0 1 Port B register
1 1 0 Control register
1 1 1 Status register
Programmable Interface
• Information in each port can be assigned a meaning depending on the mode of operation of the
I/O device
→ Port A = Data; Port B = Command; Port C = Status
• CPU initializes(loads) each port by transferring a byte to the Control Register
→ Allows CPU can define the mode of operation of each port
→ Programmable Port: By changing the bits in the control register, it is possible to change the
interface characteristics
 Asynchronous Data Transfer
Synchronous and Asynchronous Operations
Synchronous - All devices derive the timing
information from common clock line
Asynchronous - No common clock

Asynchronous Data Transfer

Asynchronous data transfer between two independent units requires that
control signals be transmitted between the communicating units to
indicate the time at which data is being transmitted
Two Asynchronous Data Transfer Methods
Strobe pulse
• A strobe pulse is supplied by one unit to indicate the other unit when the
transfer has to occur
Handshaking
• A control signal is accompanied with each data being transmitted to indicate the
presence of data
• The receiving unit responds with another control signal to acknowledge receipt
of the data
 Strobe Control

• Employs a single control line to time each transfer

• The strobe may be activated by either the source or the destination unit

Source-Initiated Strobe Destination-Initiated Strobe

for Data Transfer for Data Transfer

Block Diagram Block Diagram

Data bus Data bus
Source Destination Source Destination
unit Strobe unit unit Strobe unit

Timing Diagram Timing Diagram

Valid data Valid data
Data Data

Strobe Strobe
 Handshaking

Strobe Methods
• Source-Initiated
The source unit that initiates the transfer has no way of knowing
whether the destination unit has actually received data
• Destination-Initiated
The destination unit that initiates the transfer no way of knowing
whether the source has actually placed the data on the bus

To solve this problem, the HANDSHAKE method introduces a second

control signal to provide a Reply to the unit that initiates the transfer
 Source-Initiated Transfer using Handshake
Data bus
Source Data valid Destination
Block Diagram unit Data accepted unit

Valid data
Data bus

Timing Diagram
Data valid

Data accepted

Source unit Destination unit

Place data on bus.
Enable data valid.
Accept data from bus.
Sequence of Events Enable data accepted
Disable data valid.
Invalidate data on bus.
Disable data accepted.
Ready to accept data
(initial state).

• Allows arbitrary delays from one state to the next

• Permits each unit to respond at its own data transfer rate
• The rate of transfer is determined by the slower unit
 Destination-Initiated Transfer using Handshake
Data bus
Source Data valid Destination
Block Diagram unit unit
Ready for data

Ready for data

Timing Diagram
Data valid

Valid data
Data bus

Source unit Destination unit

Ready to accept data.
Place data on bus. Enable ready for data.
Sequence of Events Enable data valid.

Accept data from bus.

Disable data valid. Disable ready for data.
Invalidate data on bus
(initial state).

• Handshaking provides a high degree of flexibility and reliability because the successful
completion of a data transfer relies on active participation by both units
• If one unit is faulty, data transfer will not be completed
-> Can be detected by means of a timeout mechanism
 Data Transfer Technique

• Microprocessor Controlled
– Data transfer from/to I/O to/from CPU or memory
– 2 schemes
• Programmed
• Interrupt Control
• Device Controlled
– I/O device controls data transfer between I/O and memory without
CPU intervention
• Faster transfer rate
• More efficient system
 Programmed Data Transfer
• The control of programs are stored in memory
• Typically the transfer is between two programmable
registers, a CPU register and another attached to the IO Issue read command to IO module
device.
• Executed by the CPU for synchronous and asynchronous
mode of transfer Read status of IO module
• Types
– unconditional
– polling
– using Ready Signal Check
– with Handshake Signal status

• The programmed I/O transfer method is quite inefficient

A typical computer can execute 2 instructions that read Read word from IO module
and check status in 1 micro second. Assume that the
input device transfers its data at an average rate of 100
bytes per sec. The CPU will then check the flag 10000 Write word into memory
times between each transfer and time is wasted while
checking the flag instead of processing important Next
done
program instruction
 Interrupt Driver Data Transfer
• Drawbacks
– The IO transfer rates is limited by the speed Issue read command to IO
module
by which the CPU can test and service a
device.
Read status of IO module
– The CPU is tied up in managing an IO transfer;
a number of instruction must be executed for
each IO transfer. Check
status
Interrupt IO frees up the CPU to some extent at
READY
the expense of IO transfer rate, but still has an
adverse impact on CPU activity and IO transfer Read word from IO module

rate.
Write word into memory

Next
done instruction
NO
 Device Controlled Data Transfer

• The transfer of data between the mass storage device and a system
memory is often limited by the speed of microprocessor. Removing the
CPU during such a transfer and letting the peripheral manage the transfer
to or from memory would improve the speed of transfer and hence will
make the system more efficient.
• The technique is called Direct Memory Access (DMA) Data Transfer.
During DMA transfer the CPU is idle, so it has no longer control on the
system buses. A DMA Controller takes over the buses and manage the
transfer directly between the peripheral and the memory. The CPU regains
the control of buses after data transfer. DMA is faster than previous data
transfer scheme.
• CPU is free to perform operations that do not use system buses.
 Block Diagram DMA Controller
Interrupt
RAM
BG
C.P.U
BR
RD WR ADD DATA
RD WR ADD DATA
READ CONTROL

DATA BUS

ADDRESS BUS
ADDR

RD WR ADD DATA
DMA
DS ACK IO
RS DMA CONTROLLER PERIPHERAL
BR (BusRelease) DMA DEVICE
BG (BusGrant)

INTERRUPT
 Direct Memory Access
• The CPU communicates with the DMA through the address and data buses as with any
interface unit
• The DMA has its own address which activates the DS and RS lines
• The CPU initializes the DMA through data lines
• Once the DMA receives the start control command it can start the transfer between the
peripheral devices and memory
• When the peripheral device sends a DMA request the DMA controller activates the BR
line, informing the CPU to relinquish the busses
• The CPU responds with its BG lines informing the DMA that its busses are disabled
• The DMA then puts the current value of its address register into the address bus,
initiates the WR or RD signal and then sends the DMA ACK to the peripheral device
• RD and WR lines are bi-directional
• When the peripheral device receives a DMA ACK it puts a word in the data bus or
receives a word from the data bus. For READ when BG=0 the RD and WR are input lines
and acts in master mode and when BG=1 it acts as an output line from the DMA
controller to the RAM. Thus the DMA controls the read and write operation and
supplies the address for the memory.
 DMA Types
DMA types
• Burst mode of data transfer
– The IO device withdraws the DMA request only after it has transferred
all the bytes
– Block of data is transferred
– Used mainly in Magnetic Disk Drive
– The CPU is rendered inactive for relatively long periods of time
• Cycle Stealing mode of data transfer
– A long block of data is transferred by a sequence of DMA cycle
– After transferring one byte or several bytes the I/O device withdraws
DMA request
– Reduces interference in CPU activities
Universal Asynchronous Receiver-Transmitter (UART)
A typical asynchronous communication interface available as an IC
Transmit
Bidirectional Transmitter Shift data
data bus Bus register register
buffers

Control Transmitter Transmitter

clock
register control
Internal Bus
and clock
Chip select CS
Register select Status Receiver Receiver CS RS Oper. Register selected
RS Timing clock
register control 0 x x None
I/O read and and clock 1 0 WR Transmitter register
RD Control 1 1 WR Control register
I/O write Receive 1 0 RD Receiver register
WR Receiver Shift data
1 1 RD Status register
register register

Transmitter Register
• Accepts a data byte(from CPU) through the data bus
• Transferred to a shift register for serial transmission
Receiver
• Receives serial information into another shift register
• Complete data byte is sent to the receiver register
Status Register Bits
• Used for I/O flags and for recording errors
Control Register Bits
• Define baud rate, no. of bits in each character, whether to generate and check parity, and
no. of stop bits
 8251 USART Interface

Universal Synchronous Asynchronous Receiver-Transmitter (USART)

8251 RS232
D[7:0] TxD

RD RD RxD
WR WR
A0 C/D
TxC
CLK CLK RxC

A7
A6
A5
A4
A3
A2
A1
IO/M
8251 Schematic
 Programming 8251
8251 command register

EH IR RTS ER SBRK RxE DTR TxE command register

TxE: transmit enable

DTR: data terminal ready, DTR pin will be low
RxE: receiver enable
SBPRK: send break character, TxD pin will be low
ER: error reset
RTS: request to send, CTS pin will be low
IR: internal reset
EH: enter hunt mode 8251 mode register

7 6 5 4 3 2 1 0 Mode register

Number of Baud Rate

Stop bits Parity enable
0: disable 00: Syn. Mode
00: invalid 1: enable 01: x1 clock
01: 1 bit 10: x16 clock
10: 1.5 bits Character length 11: x64 clock
11: 2 bits
00: 5 bits
01: 6 bits
Parity 10: 7 bits
0: odd 11: 8 bits
1: even
 Programming 8251

8251 status register

DSR SYNDET FE OE PE TxEMPTY RxRDY TxRDY status register

TxRDY: transmit ready

RxRDY: receiver ready
TxEMPTY: transmitter empty
PE: parity error
OE: overrun error
FE: framing error
SYNDET: sync. character detected
DSR: data set ready
 Simple Serial I/O Procedures

• Read • Write

start start

Check RxRDY Check TxRDY

No No
Is it logic 1? Is it logic 1?

Yes Yes
Read data register* Write data register*

end end
* This clears RxRDY * This clears TxRDY
 Errors

– Parity error: Received data has wrong error

• transmission bit flip due to noise
– Framing error: Start and stop bits not in their proper places.
• This usually results if the receiver is receiving data at the incorrect
baud rate.
– Overrun error: Data has overrun the internal receiver FIFO buffer
• Software is failing to read the data from the FIFO
 Tugas
Review chip UART (merek/pabrikan bebas)
• Buat ringkasan berdasarkan diagram/skema
– Fungsi utama/dasar (minimum 10)
– Istilah-istilah yang relevan
– Pemanfaatan dalam rangkaian elektronik
– Pendapat/komentar anda
• Kerja individu
• Maksimum 3 halaman
• Unggah ke Elisa