Lecture No 7

Combinational Logic Design

Chapter 3 1
Selecting

Chapter 3 2
Selecting
 Selecting of data or information is a critical
function in digital systems and computers
 Circuits that perform selecting have:
• A set of information inputs from which the selection
is made
• A single output
• A set of control lines for making the selection
 Logic circuits that perform selecting are called
multiplexers

Chapter 3 3
Multiplexers
 A multiplexer selects information from an
input line and directs the information to
an output line
 A typical multiplexer has n control inputs
(Sn - 1, … S0) called selection inputs, 2n
information inputs (I2n - 1, … I0), and one
output Y
 A multiplexer can be designed to have m
information inputs with m < 2n as well as
n selection inputs
Chapter 3 4
2-to-1-Line Multiplexer
 Since 2 = 21, n = 1
 The single selection variable S has two values:
• S = 0 selects input I0
• S = 1 selects input I1
 The equation:
Y = S I0 + SI1
Enabling
 The circuit: Decoder Circuits

I0
Y
S
I1

Chapter 3 5
2-to-1-Line Multiplexer (continued)
 Note the regions of the multiplexer circuit shown:
• 1-to-2-line Decoder
• 2 Enabling circuits
• 2-input OR gate
 To obtain a basis for multiplexer expansion, we
combine the Enabling circuits and OR gate into a 2  2
AND-OR circuit:
• 1-to-2-line decoder
• 2  2 AND-OR
 In general, for an 2n-to-1-line multiplexer:
• n-to-2n-line decoder
• 2n  2 AND-OR

Chapter 3 6
 Example: 4-to-1-line Multiplexer
S1 S0 Y
0 0 I0
0 1 I1 I0
1 0 I2
I1
1 1 I3 Y
I2

I3

S1 S0

Chapter 3 7
Example: 4-to-1-line Multiplexer
 2-to-22-line decoder
 22  2 AND-OR
Decoder
S1

4 3 2 AND-OR
S0
Decoder
S1

S0
I0

Y
I1
Y

I2

I3
Chapter 3 8
Quad 2-to-1 MUX
A3
Y3
A2
Y2
A1
Y1
A0
Y0
B3

B2

B1

B0

E S Output
S E
0 X All Zeros
1 0 Select A’s
1 1 Select B’s
Chapter 3 9
Quad 2-to-1 MUX
 Think of 4 Multiplexers capable of
selecting one of two input lines

Chapter 3 10
 Combinational Logic Implementation
using Multiplexer
 Example
F(x, y, z) = ∑(1, 2, 6, 7)

Chapter 3 11
Combinational Logic Implementation
using Multiplexer

Chapter 3 12
Combinational Logic Implementation
using Multiplexer

Chapter 3 13
General Procedure

 General Procedure for implementing

Boolean with Multiplexer ?

Chapter 3 14
 Combinational Logic Implementation
using Multiplexer

F(A,B,C,D)=∑m(1,3,4,11,12,13,14,15)

Chapter 3 15
Combinational Logic Implementation
using MUX

Chapter 3 16
DEMUX

Chapter 3 17
DEMUX
Y3
S1 S0 Y3 Y2 Y 1 Y0
Y2
0 0 0 0 0 I I
Y1
0 1 0 0 I 0
1 0 0 I 0 0 Y0

1 1 I 0 0 0
S1
S0

Chapter 3 18
Combinational Logic Implementation
using Decoder

Chapter 3 19
Decoder Examples
 1-to-2-Line Decoder A D0 D1
D0 5 A
0 1 0
1 0 1 A D1 5 A
 2-to-4-Line Decoder (a) (b)
A0
A1 A0 D0 D1 D2 D3
A1
0 0 1 0 0 0 D0 5 A 1 A 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1 D1 5 A 1 A 0

(a)
D2 5 A 1 A 0
 Note that the 2-4-line
made up of 2 1-to-2- D3 5 A 1 A 0
line decoders and 4 AND gates.
(b)
Chapter 3 20
Decoder Examples

Chapter 3 21
TT For Binary Adder

Chapter 3 22
Implementing Binary adder using decoder

Chapter 3 23
Binary Adders
 Half adder
 Full Adder
 Binary Ripple Carry Adder
 Carry Look ahead Adder

Chapter 3 24
4 bit Ripple Carry Adder
0110
1011
0011
1110

A four-bit Ripple Carry Adder made from four 1-bit Full Adders
This can be used as a typical building block
Chapter 3 25
Binary Subtraction
 Algorithm:
• Subtract the subtrahend N from the minuend M
• If no end borrow occurs, then M  N, and the result
is a non-negative number and correct.
• If an end borrow occurs, the N > M and the
difference M - N + 2n is subtracted from 2n, and a
minus sign is appended to the result.
0 1
 Examples:
1001 0100
- 0111 - 0111
0010 1101
10000
- 1101
(-) 0011 Chapter 3 26
Binary Subtraction
 Solve Following Example
01100100
-10010110

Chapter 3 27
Binary Subtraction
 Solve Following Example
01100100
-10010110
11001110

100000000
-11001110
- 00110010

Chapter 3 28
Binary Subtraction (continued)
 The subtraction, 2n - N, is taking the 2’s
complement of N
 To do both addition and subtraction requires:
 Quite complex!
 Goal: Shared simpler
logic for both addition
and subtraction
 Introduce complements
as an approach

Chapter 3 29
Binary Adder Subtractor

Chapter 3 30
Complements
 Two complements:
• Diminished Radix Complement of N
 (r - 1)’s complement for radix r
 1’s complement for radix 2
 Defined as (rn - 1) - N
• Radix Complement
 r’s complement for radix r
 2’s complement in binary
 Defined as rn - N
 Subtraction is done by adding the complement of
the subtrahend
 If the result is negative, takes its 2’s complement
Chapter 3 31
Binary 1's Complement
 For r = 2, N = 011100112, n = 8 (8 digits):
(rn – 1) = 256 -1 = 25510 or 111111112
 The 1's complement of 011100112 is then:
11111111
– 01110011
10001100
 Since the 2n – 1 factor consists of all 1's and
since 1 – 0 = 1 and 1 – 1 = 0, the one's
complement is obtained by complementing
each individual bit (bitwise NOT).

Chapter 3 32
Binary 2's Complement
 For r = 2, N = 011100112, n = 8 (8 digits),
we have:
(rn ) = 25610 or 1000000002
 The 2's complement of 01110011 is then:
100000000
– 01110011
10001101
 Note the result is the 1's complement plus
1, a fact that can be used in designing
hardware
Chapter 3 33
Alternate 2’s Complement Method
 Given: an n-bit binary number, beginning at the
least significant bit and proceeding upward:
• Copy all least significant 0’s
• Copy the first 1
• Complement all bits thereafter.
 2’s Complement Example:
10010100
• Copy underlined bits:
100
• and complement bits to the left:
01101100

Chapter 3 34
Subtraction with 2’s Complement
 For n-digit, unsigned numbers M and N, find M
- N in base 2:
• Add the 2's complement of the subtrahend N to
the minuend M:
M + (2n - N) = M - N + 2n
• If M  N, the sum produces end carry rn which is
discarded; from above, M - N remains.
• If M < N, the sum does not produce an end carry
and, from above, is equal to 2n - ( N - M ), the 2's
complement of ( N - M ).
• To obtain the result - (N – M) , take the 2's
complement of the sum and place a - to its left.

Chapter 3 35
Unsigned 2’s Complement Subtraction Example 1

 Find 010101002 – 010000112

01010100 1 01010100
– 01000011 2’s comp + 10111101
00010001
 The carry of 1 indicates that no
correction of the result is required.

Chapter 3 36
Unsigned 2’s Complement Subtraction Example 2

 Find 010000112 – 010101002

0
01000011 01000011
– 01010100 2’s comp + 10101100
11101111 2’s comp
00010001
 The carry of 0 indicates that a correction
of the result is required.
 Result = – (00010001)

Chapter 3 37
Signed Integers
 Positive numbers and zero can be represented by
unsigned n-digit, radix r numbers. We need a
representation for negative numbers.
 To represent a sign (+ or –) we need exactly one more
bit of information (1 binary digit gives 21 = 2 elements
which is exactly what is needed).
 Since computers use binary numbers, by convention,
the most significant bit is interpreted as a sign bit:
s an–2  a2a1a0
where:
s = 0 for Positive numbers
s = 1 for Negative numbers
and ai = 0 or 1 represent the magnitude in some form.
Chapter 3 38
Signed Integer Representations

Signed-Magnitude – here the n – 1 digits are

interpreted as a positive magnitude.
Signed-Complement – here the digits are
interpreted as the rest of the complement of the
number. There are two possibilities here:
• Signed 1's Complement
 Uses 1's Complement Arithmetic
• Signed 2's Complement
 Uses 2's Complement Arithmetic

Chapter 3 39
Signed Integer Representation
Example
 r =2, n=3

Number Sign -Mag. 1's Comp. 2's Comp.

+3 011 011 011
+2 010 010 010
+1 001 001 001
+0 000 000 000
–0 100 111 —
–1 101 110 111
–2 110 101 110
–3 111 100 101
–4 — — 100

Chapter 4 40
Signed-Magnitude Arithmetic
 For Addition of two nos M+N
 If the sign are same , we add two
magnitude and give results sign of M
 IF Sign are different , we subtract N from
M
 End Borrow Determines Sign
 And Determine whether 2’s complement
correction is required or not.

Chapter 4 41
Sign-Magnitude Arithmetic
Example
 0 0011001
 + 1 0100101
0011001
0100101
1110100
Taking 2’s Complement
0001100
and adding sign
1 0001100
Chapter 4 42
Signed-Complement Arithmetic
 Addition using 2’s Complement:
1. Represent negative no’s in 2’s complement
form
2. Add two no’s including sign bits
3. Carry out of sign bit position is discarded
Example 1
 00000110 (6)
+ 00001101 (13)
00010011

Chapter 4 43
Addition using 2’s Complement
Examples
 Example 2: 11111010 (-6)
+00001101 (13)

 Example 3: 11111010 (-6)

11110011 (-13)

Chapter 4 44
Signed-Complement
Arithmetic
 Subtraction using 2’s Complement
1. Represent negative no’s in 2’s complement form
2. Take 2’s complement of subtrahend
3. Add it to minued
4. A Carry out of sign bit position is discarded
Example
-6 11111010
-13 - 11110011

Chapter 3 45
Subtraction using 2’s Complement
Examples
-6 11111010
-13 - 11110011

-6-(-13) = +7
-6 11111010
-13 - 00001101
 00000111

Chapter 3 46
 2’s Complement
Adder/Subtractor
 Subtraction can be done by addition of the 2's Complement.
1. Complement each bit (1's Complement.)
2. Add 1 to the result.
 The circuit shown computes A + B and A – B:
 For S = 1, subtract,
B A B A B A B A
the 2’s complement 3 3 2 2 1 1 0 0

of B is formed by using S

XORs to form the 1’s

comp and adding the 1
applied to C0.
 For S = 0, add, B is
C 3 C C 2 C 1 0
FA FA FA FA

passed through
unchanged 4C S
3 S 2S S 1 0

Chapter 4 47
Overflow Detection
 Overflow occurs if n + 1 bits are required to contain the
result from an n-bit addition or subtraction
 Overflow can occur for:
• Addition of two operands with the same sign
• Subtraction of operands with different signs
 Signed number overflow cases with correct result sign
0 0 1 1
+0 -1 - 0 +1
0 0 1 1
 Detection can be performed by examining the result
signs which should match the signs of the top operand

Chapter 4 48
Overflow Detection
 Signed number cases with carries Cn and Cn-1 shown for correct
result signs:
0 00 01 11 1
0 0 1 1
+ 0 -1 - 0 + 1
0 0 1 1
 Signed number cases with carries shown for erroneous result signs
(indicating overflow):
0 10 11 01 0
0 0 1 1
+ 0 - 1 -0 + 1
1 1 0 0
 Simplest way to implement overflow V = Cn + Cn - 1
 This works correctly only if 1’s complement and the addition of the
carry in of 1 is used to implement the complementation! Otherwise
fails for - 10 ... 0
Chapter 4 49
Home Work and Assignment 2
 Binary Multipliers
 Carry Look ahead adder

Chapter 3 50
Assignment 2
 Q1 . Design a 8 to 3 priority Encoder
Show TT and Circuit
 Q2.Construct a 4 to 16 line decoder with
an enable in put using 2 to 4 line decoders
with enable input
 Q3. Implement Following Function with
4 to 1 Multiplexer
F(A,B,C,D) =∑m(1,3,4,11,12,13,14,15)

Chapter 3 51