Lecture 9

Sequential Circuits

Chapter 5 - Part 1 1
Overview

 Part 1 - Storage Elements and Analysis

• Introduction to sequential circuits
• Types of sequential circuits
• Storage elements
 Latches
 Flip-flops
• Sequential circuit analysis
 State tables
 State diagrams
 Equivalent states
 Part 2 - Sequential Circuit Design
 Part 3 – State Machine Design

Chapter 5 - Part 1 2
 Introduction to Sequential Circuits

Inputs Outputs
Combina-
 A Sequential tional
circuit contains: Storage
Logic
Elements
• Storage elements:
Latches or Flip-Flops Next
State State
• Combinational Logic:
 Implements a multiple-output
switching function
 Inputs are signals from the outside.
 Outputs are signals to the outside.
 Other inputs, State or Present State, are
signals from storage elements.
 The remaining outputs, Next State are
inputs to storage elements.
Chapter 5 - Part 1 3
Introduction to Sequential Circuits

Chapter 5 - Part 1 4
Introduction to Sequential Circuits

Inputs Outputs
Combina-
tional
Storage
Logic
Elements
 Combinatorial Logic Next
• Next state function State State
Next State = f(Inputs, State)
• Output function
Outputs = g(Inputs, State)
• Output function
Outputs = h(State)
 Output function type depends on specification and affects
the design significantly

Chapter 5 - Part 1 5
Types of Sequential Circuits

 Depends on the times at which:

• storage elements observe their inputs, and
• storage elements change their state
 Synchronous
• Behavior defined from knowledge of its signals at discrete
instances of time
• Storage elements observe inputs and can change state only in
relation to a timing signal (clock pulses from a clock)
 Asynchronous
• Behavior defined from knowledge of inputs an any instant of
time and the order in continuous time in which inputs change
• If clock just regarded as another input, all circuits are
asynchronous!
• Nevertheless, the synchronous abstraction makes complex
designs tractable!

Chapter 5 - Part 1 6
Types of Sequential Circuits

 Asynchronous Storage circuits are

Latches.
 Synchronous Storage circuits are Flip
Flops

Chapter 5 - Part 1 7
Gate Delay and Information Storage

Chapter 5 - Part 1 8
Information Storage

 BUffer with Dealy

 Practically we want to store information
for indefinite time
 And Stored value to be changed based on
inputs
 Stored Value should not depend upon
time delay of gate.
 Consider Buffer connected in loop
 Storage can be constructed from logic
with delay connected in loop. Chapter 5 - Part 1 9
Information Storage

 NO way for information to be changed in

invertors
 Replace with NAND and NOR Gates.
 Asynchoronous circuits are made in this
manner and are called Latches.
 Complex Asynchoronous circuits are
difficult to design
 Synchoronous circuits are choice of
design
 Used to build Sysnchoronous circuits
Chapter 5 - Part 1 10
Synchoronous Cloclked Sequential
Circuits

Chapter 5 - Part 1 11
LATCHES

 A storage element that can store binary

state indefinitely untill directed by input
signal to switch the states (Power
Constraint)
 SR Latch Derived from Buffer (Two
Invertors)

Chapter 5 - Part 1 12
Basic (NOR) S – R Latch

 Cross-coupling two
NOR gates gives the
S – R Latch:
 Which has the time
sequence
behavior:
 S = 1, R = 1 is
forbidden as
input pattern

Chapter 5 - Part 1 13
Basic (NOR) S – R Latch

Chapter 5 - Part 1 14
Latches
 SR Latch S R Q0 Q Q’
Q = Q0

0 0 0 0 1

0 0
R Q

S Q
0 1

Initial Value

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Latches
 SR Latch S R Q0 Q Q’
Q = Q0
0 0 0 0 1
Q = Q0
0 0 1 1 0

0 1
R Q

S Q
0 0

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Latches
 SR Latch S R Q0 Q Q’
0 0 0 0 1 Q = Q0

0 0 1 1 0
Q=0
0 1 0 0 1
1 0
R Q

S Q
0 1

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Latches
 SR Latch S R Q0 Q Q’
0 0 0 0 1 Q = Q0

0 0 1 1 0
Q=0
0 1 0 0 1
1 1 Q=0

R Q
0 1 1 0 1

S Q
0 0

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Latches
 SR Latch S R Q0 Q Q’
0 0 0 0 1 Q = Q0

0 0 1 1 0
0 1 0 0 1 Q=0

0 0
R Q
0 1 1 0 1
Q=1

1 0 0 1 0

S Q
1 1

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Latches
 SR Latch S R Q0 Q Q’
0 0 0 0 1 Q = Q0

0 0 1 1 0
0 1 0 0 1 Q=0

0 1
R Q
0 1 1 0 1
Q=1

1 0 0 1 0
1 0 1 1 0 Q=1

S Q
1 0

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Latches
 SR Latch S R Q0 Q Q’
0 0 0 0 1 Q = Q0

0 0 1 1 0
0 1 0 0 1 Q=0

1 0
R Q
0 1 1 0 1
1 0 0 1 0 Q=1

1 0 1 1 0
Q = Q’

1 1 0 0 0

S Q
1 10

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Latches
 SR Latch S R Q0 Q Q’
0 0 0 0 1 Q = Q0

0 0 1 1 0
0 1 0 0 1 Q=0

1 10
R Q
0 1 1 0 1
1 0 0 1 0 Q=1

1 0 1 1 0
Q = Q’

1 1 0 0 0
Q = Q’

1 1 1 0 0
S Q
1 0

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Latches
 SR Latch
S R Q
R Q Q0 No change
0 0
Reset
0 1 0 Set
1 0 1 Invalid

S Q 1 1 Q=Q’=0

S S R Q
Q Invalid
0 0 Q=Q’=1
Set
0 1 1 Reset
1 0 0 No change
R Q
1 1 Q0
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Latches
 SR Latch
S R Q
R Q Q0 No change
0 0
Reset
0 1 0 Set
1 0 1 Invalid

S Q 1 1 Q=Q’=0

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Basic (NAND) S – R Latch

 “Cross-Coupling”
two NAND gates gives
the S -R Latch:
 Which has the time
sequence behavior:

 S = 0, R = 0 is
forbidden as
input pattern

Chapter 5 - Part 1 25
Basic (NAND) S – R Latch

Chapter 5 - Part 1 26
Basic (NAND) S – R Latch

S S’ R’ Q
Q Invalid
0 0 Q=Q’=1
Set
0 1 1 Reset
1 0 0 No change
R Q
1 1 Q0

Chapter 5 - Part 1 27
Clocked S - R Latch

 Adding two NAND S

gates to the basic Q
S - R NAND latch C
gives the clocked
S – R latch: Q
R
 Has a time sequence behavior similar to the basic S-R
latch except that the S and R inputs are only observed
when the line C is high.
 C means “control” or “clock”.
 C Acts as enable signal for two inputs

Chapter 5 - Part 1 28
Clocked S - R Latch (continued)

Chapter 5 - Part 1 29
D Latch – Clocked or controlled D
Latch
 To Eliminate undesirable undefined state.
 Ensure that s and R and
 Adding an inverter to the S-R Latch, gives the
D Latch:
 Note that there are no
indeterminate/Undefined”
states!
 C=0 both inputs are 1 and circuit cannot
change state.

Chapter 5 - Part 1 30
D Latch

Chapter 5 - Part 1 31
D Latch
 D Latch (D = Data) Timing Diagram

C
D S
Q
D
C
R Q
Q

t
C D Q
Output may change
0 x Q0 No change
Reset
1 0 0 Set
1 1 1

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D Latch
 D Latch (D = Data) Timing Diagram

C
D S
Q
D
C
R Q
Q

C D Q Output may change

0 x Q0 No change
Reset
1 0 0 Set
1 1 1

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Flip-Flops

 The latch timing problem

 Master-slave flip-flop
 Edge-triggered flip-flop
 Standard symbols for storage elements
 Direct inputs to flip-flops

Chapter 5 - Part 1 34
The Latch Timing Problem

 In a sequential circuit, paths may exist through

combinational logic:
• From one storage element to another
• From a storage element back to the same storage
element
 The combinational logic between a latch output
and a latch input may be as simple as an
interconnect
 For a clocked D-latch, the output Q depends on
the input D whenever the clock input C has
value 1
Chapter 5 - Part 1 35
 The Latch Timing Problem (continued)
 Consider the following circuit:
D Q Y

Clock C Q
 Suppose that initially Y = 0.
Clock
Y
 As long as C = 1, the value of Y continues to change!
 The changes are based on the delay present on the loop
through the connection from Y back to Y.
 This behavior is clearly unacceptable.
 Desired behavior: Y changes only once per clock pulse
Chapter 5 - Part 1 36
The Latch Timing Problem (continued)

 Flip flop operate correctly when

sequential circuit apply a single clock –
prevent from being transparent.
 A solution to the latch timing problem is
to break the closed path from Y to Y
within the storage element
 The commonly-used, path-breaking
solutions replace the clocked D-latch
with:
• a master-slave flip-flop
• an edge-triggered flip-flop
Chapter 5 - Part 1 37
S-R Master-Slave Flip-Flop
 Consists of two clocked S S S
Q Q Q
S-R latches in series C C C
with the clock on the R R Q R Q Q
second latch inverted
 The input is observed
by the first latch with C = 1
 The output is changed by the second latch with C = 0
 The path from input to output is broken by the
difference in clocking values (C = 1 and C = 0).
 Undefined state when both S and R are equal to 1.
 Solution J K Flip Flop

Chapter 5 - Part 1 38
JK Master Slave Flip Flop

 Only Difference between SR and JK Flip

Flop is their response to the condition
when both inputs are equal to 1.

Chapter 5 - Part 1 39
Flip-Flop Problem
 The change in the flip-flop output is delayed by
the pulse width which makes the circuit slower or
 Master Slave Flip Flop also Called Pulse
Triggered Flip Flop ; can respond to input values
that can cause a change in state and occur
anytime during the pulse

Chapter 5 - Part 1 40
Flip Flop Problem

 S and/or R are permitted to change while C = 1

• Suppose Q = 0 and S goes to 1 and then back to 0
with R remaining at 0
 The master latch sets to 1
 A 1 is transferred to the slave
• Suppose Q = 0 and S goes to 1 and back to 0 and R
goes to 1 and back to 0
 The master latch sets and then resets
 A 0 is transferred to the slave
• This behavior is called 1s catching

Chapter 5 - Part 1 41
Flip-Flop Solution

 Use edge-triggering instead of master-slave

 An edge-triggered flip-flop ignores the pulse
while it is at a constant level and triggers only
during a transition of the clock signal
 Edge-triggered flip-flops can be built directly at
the electronic circuit level, or
 A master-slave D flip-flop which also exhibits
edge-triggered behavior can be used.

Chapter 5 - Part 1 42
Flip-Flops solutions
 Controlled latches are level-triggered

 Flip-Flops are edge-triggered

CLK Positive Edge

CLK Negative Edge

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 Edge-Triggered D Flip-Flop
 The edge-triggered D D S
Q Q Q
D flip-flop is the
C
same as the master- C C Q R Q Q
slave D flip-flop
 It can be formed by:
• Replacing the first clocked S-R latch with a clocked D latch or
• Adding a D input and inverter to a master-slave S-R flip-flop
 The delay of the S-R master-slave flip-flop can be
avoided since the 1s-catching behavior is not present
with D replacing S and R inputs
 The change of the D flip-flop output is associated with
the negative edge at the end of the pulse
 It is called a negative-edge triggered flip-flop
Chapter 5 - Part 1 44
 Flip-Flops
 Master-Slave D Flip-Flop
D D Q D Q Q
D Latch D Latch
C(Master) C(Slave)

Master Slave

CLK
CLK

Looks like it is negative edge-triggered QMaster

QSlave
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Positive-Edge Triggered D Flip-Flop
 Formed by D D Q S Q
Q
adding inverter C
to clock input C C Q R Q Q

 Q changes to the value on D applied at the

positive clock edge within timing constraints to
be specified
 Our choice as the standard flip-flop for most
sequential circuits

Chapter 5 - Part 1 46
Flip-FlopT
 T Flip-Flop

T Q
T J Q

Q
K Q

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Flip-Flop Characteristic Tables

D Q D Q(t+1)
0 0 Reset
Set
Q 1 1

J K Q(t+1)
J Q No change
0 0 Q(t) Reset
0 1 0 Set
1 0 1 Toggle
K Q
1 1 Q’(t)

T Q T Q(t+1)
0 Q(t) No change
Q Toggle
1 Q’(t)
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Flip-Flop Characteristic Equations

D Q D Q(t+1)
0 0 Q(t+1) = D
Q 1 1

J K Q(t+1)
J Q 0 0 Q(t)
Q(t+1) = JQ’ + K’Q
0 1 0
K Q 1 0 1
1 1 Q’(t)

T Q T Q(t+1)
0 Q(t) Q(t+1) = T  Q
Q
1 Q’(t)
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Flip-Flop Characteristic Equations
 Analysis / Derivation
J K Q(t) Q(t+1)
No change
0 0 0 0
J Q Reset
0 0 1 1
0 1 0 Set
K Q 0 1 1
Toggle
1 0 0
1 0 1
1 1 0
1 1 1

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Flip-Flop Characteristic Equations
 Analysis / Derivation
J K Q(t) Q(t+1)
No change
0 0 0 0
J Q Reset
0 0 1 1
0 1 0 0 Set
K Q 0 1 1 0
Toggle
1 0 0
1 0 1
1 1 0
1 1 1

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Flip-Flop Characteristic Equations
 Analysis / Derivation
J K Q(t) Q(t+1)
No change
0 0 0 0
J Q Reset
0 0 1 1
0 1 0 0 Set
K Q 0 1 1 0
Toggle
1 0 0 1
1 0 1 1
1 1 0
1 1 1

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Flip-Flop Characteristic Equations
 Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0
J Q
0 0 1 1 No change
0 1 0 0
Reset
K Q 0 1 1 0
1 0 0 1 Set
1 0 1 1
1 1 0 1 Toggle
1 1 1 0

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Flip-Flop Characteristic Equations
 Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0 K
J Q
0 0 1 1 0 1 0 0
0 1 0 0 J 1 1 0 1
K Q 0 1 1 0 Q
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
Q(t+1) = JQ’ + K’Q

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 Standard Symbols for Storage
Elements
S S D D

R R C C

SR SR D with 1 Control D with 0 Control

 Master-Slave:
(a) Latches

Postponed output S S D D
indicators C C
R R C C

Triggered SR Triggered SR Triggered D Triggered D

 Edge-Triggered: (b) Master-Slave Flip-Flops

Dynamic D D
indicator
C C

Triggered D Triggered D
(c) Edge-Triggered Flip-Flops
Chapter 5 - Part 1 55
Sequential Circuit Analysis

 General Model
Inputs Outputs
• Current State Combina-
at time (t) is tional
stored in an Storage Logic
array of Elements
Next
flip-flops. State State
• Next State at time (t+1)
is a Boolean function of CLK
State and Inputs.
• Outputs at time (t) are a Boolean function of
State (t) and (sometimes) Inputs (t).

Chapter 5 - Part 1 56
Analysis of Clocked Sequential
Circuits
 The State
• State = Values of all Flip-Flops

x
Example D Q A

AB=00 Q

D Q B

CLK Q

57
 Analysis of Clocked Sequential
Circuits
 State Equations
x
D Q A
A(t+1) = DA
= A(t) x(t)+B(t) x(t)
=Ax +Bx Q
B(t+1) = DB
= A’(t) x(t)
= A’ x D Q B
y(t) = [A(t)+ B(t)] x’(t)
= (A + B) x’ CLK Q

58
 Analysis of Clocked Sequential Circuits

 State Table (Transition Table)

x
Present Next D Q A
Input Output
State State
Q
A B x A B y
0 0 0 0 0 0 B
D Q
0 0 1 0 1 0
CLK Q
0 1 0 0 0 1
0 1 1 1 1 0 y

1 0 0 0 0 1
1 0 1 1 0 0
A(t+1) = A x + B x
1 1 0 0 0 1
1 1 1 1 0 0 B(t+1) = A’ x
y(t) = (A + B) x’
t t+1 t
59
Analysis of Clocked Sequential
Circuits
 State Table (Transition Table)
x
Present Next State Output D Q A

State x=0 x=1 x=0 x=1 Q

A B A B A B y y
0 0 0 0 0 1 0 0 D Q B
0 1 0 0 1 1 1 0
CLK Q
1 0 0 0 1 0 1 0
1 1 0 0 1 0 1 0 y

t t+1 t A(t+1) = A x + B x
B(t+1) = A’ x
y(t) = (A + B) x’

60
 Analysis of Clocked Sequential Circuits
 State Diagram Present Next State Output
State x=0 x=1 x=0 x=1
A B A B A B y y
AB input/output
0 0 0 0 0 1 0 0
0 1 0 0 1 1 1 0
0/0 1/0
1 0 0 0 1 0 1 0
0/1 1 1 0 0 1 0 1 0

00 10
x
D Q A
0/1
Q
1/0 0/1 1/0
D Q B

CLK Q
01 11
y

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Analysis of Clocked Sequential
Circuits
 D Flip-Flops
Example: x D Q A
y
Present Next
Input
State State CLK Q
A x y A
0 0 0 0
1
0 0 1 1 A(t+1) = DA = A  x  y
0 1 0 0
1
0 1 1 0
1 0 0 0 01,10
1
1 0 1
00,11 0 1 00,11
1 1 0
1 1 1 01,10

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 Analysis of Clocked Sequential
Circuits
 JK Flip-Flops J Q A

Example: x K Q

Present Next Flip-Flop

I/P J Q B
State State Inputs
A B x A B JA KA JB KB K Q
0 0 0 0 1 0 0 1 0
CLK
0 0 0 0 0 1
0 0 1 1 1 1 1 1 0 JA = B KA = B x’
0 1 0 1 0 1 0 0 1 JB = x’ KB = A x 

1 1 0 0 1 1
0 1 1 1 0 0 0 0 0
1 0 0 0 0 1 1 1 1 A(t+1) = JA Q’A + K’A QA
1 1 1 0 0 0 = A’B + AB’ + Ax
1 0 1 B(t+1) = JB Q’B + K’B QB
= B’x’ + ABx + A’Bx’
1 1 0
1 1 1
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 Analysis of Clocked Sequential
Circuits
 JK Flip-Flops J Q A

x K Q
Example:
Present Next Flip-Flop J Q B
I/P
State State Inputs
A B x A B JA KA JB KB K Q

0 0 0 0 1 0 0 1 0 CLK
0 0 0 0 0 1 1 0 1
0 0 1 1 1 1 1 1 0
0 1 0 1 0 1 0 0 1 00 11
1 1 0 0 1 1
0 1 1 1 0 0 0 0 0
0
1 0 0 0 0 1 1 1 1 0 0
1 1 1 0 0 0
1 0 1
1 1 0 01 10
1
1 1 1 1
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 Analysis of Clocked Sequential
Circuits
x A
 T Flip-Flops T Q y

R Q
Example:
Present Next F.F
I/P O/P
State State Inputs T Q
B
A B x A B TA TB y
0 0 R Q
0 0 0 0 0 0
0 1 0 1 0
0 0 1 0 1 0 0 0 CLK Reset
0 1 0 1 0 1 1 0
1 0 0 0 0 TA = B x TB = x
0 1 1 1 1 0 1 0 y =AB
1 0 0 1 1 0 0 1
0 0 1 1 1 A(t+1) = TA Q’A + T’A QA
1 0 1 = AB’ + Ax’ + A’Bx
1 1 0 B(t+1) = TB Q’B + T’B QB
=x B


1 1 1
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 Analysis of Clocked Sequential
Circuits
x A
 T Flip-Flops T Q y

R Q
Example:
Present Next F.F
I/P O/P
State State Inputs T Q
B
A B x A B TA TB y
0 0 R Q
0 0 0 0 0 0
0 1 0 1 0
0 0 1 0 1 0 0 0 CLK Reset
0 1 0 1 0 1 1 0 0/0 0/0
1 0 0 0 0
0 1 1 1 1 0 1 0 00
1/0 01
1 0 0 1 1 0 0 1
0 0 1 1 1 1/1 1/0
1 0 1
1 1 0 11 10
0/1 0/0
1 1 1 1/0
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