Lecture 9

Sequential Circuits

Chapter 5 - Part 1 1
Overview

 Part 1 - Storage Elements and Analysis

• Introduction to sequential circuits
• Types of sequential circuits
• Storage elements
 Latches
 Flip-flops
• Sequential circuit analysis
 State tables
 State diagrams
 Equivalent states
 Part 2 - Sequential Circuit Design
 Part 3 – State Machine Design

Chapter 5 - Part 1 2
 Introduction to Sequential Circuits

Inputs Outputs
Combina-
 A Sequential tional
circuit contains: Storage
Logic
Elements
• Storage elements:
Latches or Flip-Flops Next
State State
• Combinational Logic:
 Implements a multiple-output
switching function
 Inputs are signals from the outside.
 Outputs are signals to the outside.
 Other inputs, State or Present State, are
signals from storage elements.
 The remaining outputs, Next State are
inputs to storage elements.
Chapter 5 - Part 1 3
Introduction to Sequential Circuits

Chapter 5 - Part 1 4
Introduction to Sequential Circuits

Inputs Outputs
Combina-
tional
Storage
Logic
Elements
 Combinatorial Logic Next
• Next state function State State
Next State = f(Inputs, State)
• Output function
Outputs = g(Inputs, State)
• Output function
Outputs = h(State)
 Output function type depends on specification and affects
the design significantly

Chapter 5 - Part 1 5
Types of Sequential Circuits

 Depends on the times at which:

• storage elements observe their inputs, and
• storage elements change their state
 Synchronous
• Behavior defined from knowledge of its signals at discrete
instances of time
• Storage elements observe inputs and can change state only in
relation to a timing signal (clock pulses from a clock)
 Asynchronous
• Behavior defined from knowledge of inputs an any instant of
time and the order in continuous time in which inputs change
• If clock just regarded as another input, all circuits are
asynchronous!
• Nevertheless, the synchronous abstraction makes complex
designs tractable!

Chapter 5 - Part 1 6
Types of Sequential Circuits

 Asynchronous Storage circuits are

Latches.
 Synchronous Storage circuits are Flip
Flops

Chapter 5 - Part 1 7
Gate Delay and Information Storage

Chapter 5 - Part 1 8
Information Storage

 BUffer with Dealy

 Practically we want to store information
for indefinite time
 And Stored value to be changed based on
inputs
 Stored Value should not depend upon
time delay of gate.
 Consider Buffer connected in loop
 Storage can be constructed from logic
with delay connected in loop. Chapter 5 - Part 1 9
Information Storage

 NO way for information to be changed in

invertors
 Replace with NAND and NOR Gates.
 Asynchoronous circuits are made in this
manner and are called Latches.
 Complex Asynchoronous circuits are
difficult to design
 Synchoronous circuits are choice of
design
 Used to build Sysnchoronous circuits
Chapter 5 - Part 1 10
Synchoronous Cloclked Sequential
Circuits

Chapter 5 - Part 1 11
LATCHES

 A storage element that can store binary

state indefinitely untill directed by input
signal to switch the states (Power
Constraint)
 SR Latch Derived from Buffer (Two
Invertors)

Chapter 5 - Part 1 12
Basic (NOR) S – R Latch

 Cross-coupling two
NOR gates gives the
S – R Latch:
 Which has the time
sequence
behavior:
 S = 1, R = 1 is
forbidden as
input pattern

Chapter 5 - Part 1 13
Basic (NOR) S – R Latch

Chapter 5 - Part 1 14
Latches
 SR Latch S R Q0 Q Q’
Q = Q0

0 0 0 0 1

0 0
R Q

S Q
0 1

Initial Value

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Latches
 SR Latch S R Q0 Q Q’
Q = Q0
0 0 0 0 1
Q = Q0
0 0 1 1 0

0 1
R Q

S Q
0 0

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Latches
 SR Latch S R Q0 Q Q’
0 0 0 0 1 Q = Q0

0 0 1 1 0
Q=0
0 1 0 0 1
1 0
R Q

S Q
0 1

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Latches
 SR Latch S R Q0 Q Q’
0 0 0 0 1 Q = Q0

0 0 1 1 0
Q=0
0 1 0 0 1
1 1 Q=0

R Q
0 1 1 0 1

S Q
0 0

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Latches
 SR Latch S R Q0 Q Q’
0 0 0 0 1 Q = Q0

0 0 1 1 0
0 1 0 0 1 Q=0

0 0
R Q
0 1 1 0 1
Q=1

1 0 0 1 0

S Q
1 1

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Latches
 SR Latch S R Q0 Q Q’
0 0 0 0 1 Q = Q0

0 0 1 1 0
0 1 0 0 1 Q=0

0 1
R Q
0 1 1 0 1
Q=1

1 0 0 1 0
1 0 1 1 0 Q=1

S Q
1 0

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Latches
 SR Latch S R Q0 Q Q’
0 0 0 0 1 Q = Q0

0 0 1 1 0
0 1 0 0 1 Q=0

1 0
R Q
0 1 1 0 1
1 0 0 1 0 Q=1

1 0 1 1 0
Q = Q’

1 1 0 0 0

S Q
1 10

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Latches
 SR Latch S R Q0 Q Q’
0 0 0 0 1 Q = Q0

0 0 1 1 0
0 1 0 0 1 Q=0

1 10
R Q
0 1 1 0 1
1 0 0 1 0 Q=1

1 0 1 1 0
Q = Q’

1 1 0 0 0
Q = Q’

1 1 1 0 0
S Q
1 0

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Latches
 SR Latch
S R Q
R Q Q0 No change
0 0
Reset
0 1 0 Set
1 0 1 Invalid

S Q 1 1 Q=Q’=0

S S R Q
Q Invalid
0 0 Q=Q’=1
Set
0 1 1 Reset
1 0 0 No change
R Q
1 1 Q0
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Latches
 SR Latch
S R Q
R Q Q0 No change
0 0
Reset
0 1 0 Set
1 0 1 Invalid

S Q 1 1 Q=Q’=0

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Basic (NAND) S – R Latch

Chapter 5 - Part 1 25
Basic (NAND) S – R Latch

S S’ R’ Q
Q Invalid
0 0 Q=Q’=1
Set
0 1 1 Reset
1 0 0 No change
R Q
1 1 Q0

Chapter 5 - Part 1 26
Clocked S - R Latch

 Adding two NAND S

gates to the basic Q
S - R NAND latch C
gives the clocked
S – R latch: Q
R
 Has a time sequence behavior similar to the basic S-R
latch except that the S and R inputs are only observed
when the line C is high.
 C means “control” or “clock”.
 C Acts as enable signal for two inputs

Chapter 5 - Part 1 27
Basic (NAND) S – R Latch

 “Cross-Coupling”
two NAND gates gives
the S -R Latch:
 Which has the time
sequence behavior:

 S = 0, R = 0 is
forbidden as
input pattern

Chapter 5 - Part 1 28
Clocked S - R Latch (continued)

Chapter 5 - Part 1 29
D Latch – Clocked or controlled D
Latch
 To Eliminate undesirable undefined state.
 Ensure that s and R and
 Adding an inverter to the S-R Latch, gives the
D Latch:
 Note that there are no
indeterminate/Undefined”
states!
 C=0 both inputs are 1 and circuit cannot
change state.

Chapter 5 - Part 1 30
D Latch

Chapter 5 - Part 1 31
D Latch
 D Latch (D = Data) Timing Diagram

C
D S
Q
D
C
R Q
Q

t
C D Q
Output may change
0 x Q0 No change
Reset
1 0 0 Set
1 1 1

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D Latch
 D Latch (D = Data) Timing Diagram

C
D S
Q
D
C
R Q
Q

C D Q Output may change

0 x Q0 No change
Reset
1 0 0 Set
1 1 1

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Flip-Flops

 The latch timing problem

 Master-slave flip-flop
 Edge-triggered flip-flop
 Standard symbols for storage elements
 Direct inputs to flip-flops

Chapter 5 - Part 1 34
The Latch Timing Problem

 In a sequential circuit, paths may exist through

combinational logic:
• From one storage element to another
• From a storage element back to the same storage
element
 The combinational logic between a latch output
and a latch input may be as simple as an
interconnect
 For a clocked D-latch, the output Q depends on
the input D whenever the clock input C has
value 1
Chapter 5 - Part 1 35
 The Latch Timing Problem (continued)
 Consider the following circuit:
D Q Y

Clock C Q
 Suppose that initially Y = 0.
Clock
Y
 As long as C = 1, the value of Y continues to change!
 The changes are based on the delay present on the loop
through the connection from Y back to Y.
 This behavior is clearly unacceptable.
 Desired behavior: Y changes only once per clock pulse
Chapter 5 - Part 1 36
The Latch Timing Problem (continued)

 Flip flop operate correctly when

sequential circuit apply a single clock –
prevent from being transparent.
 A solution to the latch timing problem is
to break the closed path from Y to Y
within the storage element
 The commonly-used, path-breaking
solutions replace the clocked D-latch
with:
• a master-slave flip-flop
• an edge-triggered flip-flop
Chapter 5 - Part 1 37
S-R Master-Slave Flip-Flop
 Consists of two clocked S S S
Q Q Q
S-R latches in series C C C
with the clock on the R R Q R Q Q
second latch inverted
 The input is observed
by the first latch with C = 1
 The output is changed by the second latch with C = 0
 The path from input to output is broken by the
difference in clocking values (C = 1 and C = 0).
 Undefined state when both S and R are equal to 1.
 Solution J K Flip Flop

Chapter 5 - Part 1 38
JK Master Slave Flip Flop

 Only Difference between SR and JK Flip

Flop is their response to the condition
when both inputs are equal to 1.

Chapter 5 - Part 1 39
Flip-Flop Problem
 The change in the flip-flop output is delayed by
the pulse width which makes the circuit slower or
 Master Slave Flip Flop also Called Pulse
Triggered Flip Flop ; can respond to input values
that can cause a change in state and occur
anytime during the pulse

Chapter 5 - Part 1 40
Flip Flop Problem

 S and/or R are permitted to change while C = 1

• Suppose Q = 0 and S goes to 1 and then back to 0
with R remaining at 0
 The master latch sets to 1
 A 1 is transferred to the slave
• Suppose Q = 0 and S goes to 1 and back to 0 and R
goes to 1 and back to 0
 The master latch sets and then resets
 A 0 is transferred to the slave
• This behavior is called 1s catching

Chapter 5 - Part 1 41
Flip-Flop Solution

 Use edge-triggering instead of master-slave

 An edge-triggered flip-flop ignores the pulse
while it is at a constant level and triggers only
during a transition of the clock signal
 Edge-triggered flip-flops can be built directly at
the electronic circuit level, or
 A master-slave D flip-flop which also exhibits
edge-triggered behavior can be used.

Chapter 5 - Part 1 42
Flip-Flops solutions
 Controlled latches are level-triggered

 Flip-Flops are edge-triggered

CLK Positive Edge

CLK Negative Edge

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 Edge-Triggered D Flip-Flop
 The edge-triggered D D S
Q Q Q
D flip-flop is the
C
same as the master- C C Q R Q Q
slave D flip-flop
 It can be formed by:
• Replacing the first clocked S-R latch with a clocked D latch or
• Adding a D input and inverter to a master-slave S-R flip-flop
 The delay of the S-R master-slave flip-flop can be
avoided since the 1s-catching behavior is not present
with D replacing S and R inputs
 The change of the D flip-flop output is associated with
the negative edge at the end of the pulse
 It is called a negative-edge triggered flip-flop
Chapter 5 - Part 1 44
 Flip-Flops
 Master-Slave D Flip-Flop
D D Q D Q Q
D Latch D Latch
C(Master) C(Slave)

Master Slave

CLK
CLK

Looks like it is negative edge-triggered QMaster

QSlave
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Positive-Edge Triggered D Flip-Flop
 Formed by D D Q S Q
Q
adding inverter C
to clock input C C Q R Q Q

 Q changes to the value on D applied at the

positive clock edge within timing constraints to
be specified
 Our choice as the standard flip-flop for most
sequential circuits

Chapter 5 - Part 1 46
Flip-FlopT
 T Flip-Flop

T Q
T J Q

Q
K Q

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Flip-Flop Characteristic Tables

D Q D Q(t+1)
0 0 Reset
Set
Q 1 1

J K Q(t+1)
J Q No change
0 0 Q(t) Reset
0 1 0 Set
1 0 1 Toggle
K Q
1 1 Q’(t)

T Q T Q(t+1)
0 Q(t) No change
Q Toggle
1 Q’(t)
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Flip-Flop Characteristic Equations

D Q D Q(t+1)
0 0 Q(t+1) = D
Q 1 1

J K Q(t+1)
J Q 0 0 Q(t)
Q(t+1) = JQ’ + K’Q
0 1 0
K Q 1 0 1
1 1 Q’(t)

T Q T Q(t+1)
0 Q(t) Q(t+1) = T  Q
Q
1 Q’(t)
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Flip-Flop Characteristic Equations
 Analysis / Derivation
J K Q(t) Q(t+1)
No change
0 0 0 0
J Q Reset
0 0 1 1
0 1 0 Set
K Q 0 1 1
Toggle
1 0 0
1 0 1
1 1 0
1 1 1

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Flip-Flop Characteristic Equations
 Analysis / Derivation
J K Q(t) Q(t+1)
No change
0 0 0 0
J Q Reset
0 0 1 1
0 1 0 0 Set
K Q 0 1 1 0
Toggle
1 0 0
1 0 1
1 1 0
1 1 1

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Flip-Flop Characteristic Equations
 Analysis / Derivation
J K Q(t) Q(t+1)
No change
0 0 0 0
J Q Reset
0 0 1 1
0 1 0 0 Set
K Q 0 1 1 0
Toggle
1 0 0 1
1 0 1 1
1 1 0
1 1 1

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Flip-Flop Characteristic Equations
 Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0
J Q
0 0 1 1 No change
0 1 0 0
Reset
K Q 0 1 1 0
1 0 0 1 Set
1 0 1 1
1 1 0 1 Toggle
1 1 1 0

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Flip-Flop Characteristic Equations
 Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0 K
J Q
0 0 1 1 0 1 0 0
0 1 0 0 J 1 1 0 1
K Q 0 1 1 0 Q
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
Q(t+1) = JQ’ + K’Q

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 Standard Symbols for Storage
Elements
S S D D

R R C C

SR SR D with 1 Control D with 0 Control

 Master-Slave:
(a) Latches

Postponed output S S D D
indicators C C
R R C C

Triggered SR Triggered SR Triggered D Triggered D

 Edge-Triggered: (b) Master-Slave Flip-Flops

Dynamic D D
indicator
C C

Triggered D Triggered D
(c) Edge-Triggered Flip-Flops
Chapter 5 - Part 1 55
Lecture 12
Sequential Circuit Analysis &
Sequential Circuits Design

Chapter 5 - Part 1 56
Overview
 Part 1 - Sequential Circuit Analysis
• Sequential circuit analysis
 State tables
 State diagrams
 Equivalent states

 Part 2- Sequential Circuit Design

 Specification
 Formulation
 State Assignment
 Flip-Flop Input and Output Equation
Determination
 Verification

Chapter 5 - Part 2 57
Sequential Circuit Analysis

 General Model
Inputs Outputs
• Current State Combina-
at time (t) is tional
stored in an Storage Logic
array of Elements
Next
flip-flops. State State
• Next State at time (t+1)
is a Boolean function of CLK
State and Inputs.
• Outputs at time (t) are a Boolean function of
State (t) and (sometimes) Inputs (t).

Chapter 5 - Part 1 58
Analysis of Clocked Sequential
Circuits
 The State
• State = Values of all Flip-Flops

x
Example D Q A

AB=00 Q

D Q B

CLK Q

59
 Analysis of Clocked Sequential
Circuits
 State Equations
x
D Q A
A(t+1) = DA
= A(t) x(t)+B(t) x(t)
=Ax +Bx Q
B(t+1) = DB
= A’(t) x(t)
= A’ x D Q B
y(t) = [A(t)+ B(t)] x’(t)
= (A + B) x’ CLK Q

60
 Analysis of Clocked Sequential Circuits

 State Table (Transition Table)

x
Present Next D Q A
Input Output
State State
Q
A B x A B y
0 0 0 0 0 0 B
D Q
0 0 1 0 1 0
CLK Q
0 1 0 0 0 1
0 1 1 1 1 0 y

1 0 0 0 0 1
1 0 1 1 0 0
A(t+1) = A x + B x
1 1 0 0 0 1
1 1 1 1 0 0 B(t+1) = A’ x
y(t) = (A + B) x’
t t+1 t
61
Analysis of Clocked Sequential
Circuits
 State Table (Transition Table)
x
Present Next State Output D Q A

State x=0 x=1 x=0 x=1 Q

A B A B A B y y
0 0 0 0 0 1 0 0 D Q B
0 1 0 0 1 1 1 0
CLK Q
1 0 0 0 1 0 1 0
1 1 0 0 1 0 1 0 y

t t+1 t A(t+1) = A x + B x
B(t+1) = A’ x
y(t) = (A + B) x’

62
 Analysis of Clocked Sequential Circuits
 State Diagram Present Next State Output
State x=0 x=1 x=0 x=1
A B A B A B y y
AB input/output
0 0 0 0 0 1 0 0
0 1 0 0 1 1 1 0
0/0 1/0
1 0 0 0 1 0 1 0
0/1 1 1 0 0 1 0 1 0

00 10
x
D Q A
0/1
Q
1/0 0/1 1/0
D Q B

CLK Q
01 11
y

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Analysis of Clocked Sequential
Circuits
 D Flip-Flops
Example: x D Q A
y
Present Next
Input
State State CLK Q
A x y A
0 0 0 0
0 0 1 1 A(t+1) = DA = A  x  y
0 1 0 1
0 1 1 0
1 0 0 01,10
1
1 0 1 0 00,11 0 1 00,11
1 1 0 0
1 1 1 1 01,10

64
 Analysis of Clocked Sequential
Circuits
 JK Flip-Flops J Q A

Example: x K Q

Present Next Flip-Flop

I/P J Q B
State State Inputs
A B x A B JA KA JB KB K Q
0 0 0 0 1 0 0 1 0 CLK
0 0 1 0 0 0 0 0 1 JA = B KA = B x’
0 1 0 JB = x’ KB = A x 

1 1 1 1 1 0
0 1 1 1 0 1 0 0 1
1 0 0 A(t+1) = JA Q’A + K’A QA
1 1 0 0 1 1 = A’B + AB’ + Ax
1 0 1 1 0 0 0 0 0 B(t+1) = JB Q’B + K’B QB
= B’x’ + ABx + A’Bx’
1 1 0 0 0 1 1 1 1
1 1 1 1 1 1 0 0 0
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 Analysis of Clocked Sequential
Circuits
 JK Flip-Flops J Q A

x K Q
Example:
Present Next Flip-Flop J Q B
I/P
State State Inputs
A B x A B JA KA JB KB K Q

0 0 0 0 1 0 0 1 0 CLK
1 0 1
0 0 1 0 0 0 0 0 1
0 1 0 1 1 1 1 1 0 00 11

0 1 1 1 0 1 0 0 1 0
1 0 0 0 0
1 1 0 0 1 1
1 0 1 1 0 0 0 0 0
1 1 0 0 0 1 1 1 1 01 10
1
1 1 1 1 1 1 0 0 0 1
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 Analysis of Clocked Sequential
Circuits
x A
 T Flip-Flops T Q y

R Q
Example:
Present Next F.F
I/P O/P
State State Inputs T Q
B
A B x A B TA TB y
R Q
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0 CLK Reset
0 1 0 0 1 0 0 0 TA = B x TB = x
0 1 1 1 0 1 1 0 y =AB
1 0 0 1 0 0 0 0
A(t+1) = TA Q’A + T’A QA
1 0 1 1 1 0 1 0 = AB’ + Ax’ + A’Bx
1 1 0 B(t+1) = TB Q’B + T’B QB
1 1 0 0 1 =x B


1 1 1 0 0 1 1 1
67
 Analysis of Clocked Sequential
Circuits
x A
 T Flip-Flops T Q y

R Q
Example:
Present Next F.F
I/P O/P
State State Inputs T Q
B
A B x A B TA TB y
R Q
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0 CLK Reset
0 1 0 0 1 0 0 0 0/0 0/0
0 1 1 1 0 1 1 0 00
1/0 01
1 0 0 1 0 0 0 0
1/1 1/0
1 0 1 1 1 0 1 0
1 1 0 1 1 0 0 1 11 10
0/1 0/0
1 1 1 0 0 1 1 1 1/0
68
Sequential Circuit Design

Chapter 5 - Part 1 69
The Design Procedure

 Specification
 Formulation - Obtain a state diagram or state table
 State Assignment - Assign binary codes to the states
 Flip-Flop Input Equation Determination - Select flip-flop
types and derive flip-flop equations from next state entries in the
table
 Output Equation Determination - Derive output equations
from output entries in the table
 Optimization - Optimize the equations
 Technology Mapping - Find circuit from equations and map to
flip-flops and gate technology
 Verification - Verify correctness of final design

Chapter 5 - Part 2 70
Specification

 Component Forms of Specification

• Written description
• Mathematical description
• Hardware description language*
• Tabular description*
• Equation description*
• Diagram describing operation (not just structure)*
 Relation to Formulation
• If a specification is rigorous at the binary level
(marked with * above), then all or part of
formulation may be completed

Chapter 5 - Part 2 71
Formulation: Finding a State Diagram

 A state is an abstraction of the history of the past

applied inputs to the circuit (including power-up reset
or system reset).
• The interpretation of “past inputs” is tied to the synchronous
operation of the circuit. E. g., an input value (other than an
asynchronous reset) is measured only during the setup-hold
time interval for an edge-triggered flip-flop.
 Examples:
• State A represents the fact that a 1 input has occurred among
the past inputs.
• State B represents the fact that a 0 followed by a 1 have
occurred as the most recent past two inputs.

Chapter 5 - Part 2 72
Formulation: Finding a State Diagram

 In specifying a circuit, we use states to remember

meaningful properties of past input sequences that are
essential to predicting future output values.
 A sequence recognizer is a sequential circuit that
produces a distinct output value whenever a prescribed
pattern of input symbols occur in sequence, i.e,
recognizes an input sequence occurence.
 We will develop a procedure specific to sequence
recognizers to convert a problem statement into a state
diagram.
 Next, the state diagram, will be converted to a state
table from which the circuit will be designed.

Chapter 5 - Part 2 73
Sequence Recognizer Procedure
 To develop a sequence recognizer state diagram:
• Begin in an initial state in which NONE of the initial portion of
the sequence has occurred (typically “reset” state).
• Add a state that recognizes that the first symbol has occurred.
• Add states that recognize each successive symbol occurring.
• The final state represents the input sequence (possibly less the
final input value) occurence.
• Add state transition arcs which specify what happens when a
symbol not in the proper sequence has occurred.
• Add other arcs on non-sequence inputs which transition to
states that represent the input subsequence that has occurred.
 The last step is required because the circuit must recognize the
input sequence regardless of where it occurs within the overall
sequence applied since “reset.”.

Chapter 5 - Part 2 74
State Assignment

 Each of the m states must be assigned a

unique code
 Minimum number of bits required is n
such that
n ≥ log2 m
where x is the smallest integer ≥ x
 There are useful state assignments that
use more than the minimum number of
bits
 There are 2n - m unused states
Chapter 5 - Part 2 75
Sequence Recognizer Example

 Example: Recognize the sequence 1101

• Note that the sequence 1111101 contains 1101 and "11" is a
proper sub-sequence of the sequence.
 Thus, the sequential machine must remember that the
first two one's have occurred as it receives another
symbol.
 Also, the sequence 1101101 contains 1101 as both an
initial subsequence and a final subsequence with some
overlap, i. e., 1101101 or 1101101.
 And, the 1 in the middle, 1101101, is in both
subsequences.
 The sequence 1101 must be recognized each time it
occurs in the input sequence.
Chapter 5 - Part 2 76
Example: Recognize 1101

 Define states for the sequence to be recognized:

• assuming it starts with first symbol,
• continues through each symbol in the sequence to be
recognized, and
• uses output 1 to mean the full sequence has occurred,
• with output 0 otherwise.
 Starting in the initial state (Arbitrarily named
"A"):
1/0
• Add a state that A B
recognizes the first "1."
• State "A" is the initial state, and state "B" is the state which
represents the fact that the "first" one in the input
subsequence has occurred. The output symbol "0" means
that the full recognized sequence has not yet occurred.
Chapter 5 - Part 2 77
Example: Recognize 1101 (continued)
 After one more 1, we have:
• C is the state obtained
when the input sequence 1/0 1/0
has two "1"s. A B C
 Finally, after 110 and a 1, we have:

1/0 0/0
A 1/0 B C D
1/1

• Transition arcs are used to denote the output function (Mealy Model)
• Output 1 on the arc from D means the sequence has been recognized
• To what state should the arc from state D go? Remember: 1101101 ?
• Note that D is the last state but the output 1 occurs for the input
applied in D. This is the case when a Mealy model is assumed.

Chapter 5 - Part 2 78
Example: Recognize 1101 (continued)

A 1/0
B
1/0 0/0 1/1
C D
 Clearly the final 1 in the recognized sequence
1101 is a sub-sequence of 1101. It follows a 0
which is not a sub-sequence of 1101. Thus it
should represent the same state reached from the
initial state after a first 1 is observed. We obtain:

1/0 0/0
A 1/0 B C D

1/1
Chapter 5 - Part 2 79
Example: Recognize 1101 (continued)

1/0 1/0 0/0

A B C D

1/1
 The state have the following abstract meanings:
• A: No proper sub-sequence of the sequence has
occurred.
• B: The sub-sequence 1 has occurred.
• C: The sub-sequence 11 has occurred.
• D: The sub-sequence 110 has occurred.
• The 1/1 on the arc from D to B means that the last 1
has occurred and thus, the sequence is recognized.
Chapter 5 - Part 2 80
Example: Recognize 1101 (continued)

 The other arcs are added to each state for

inputs not yet listed. Which arcs are missing?

1/0 1/0 0/0

A B C D

 Answer: 1/1
"0" arc from A
"0" arc from B
"1" arc from C
"0" arc from D.

Chapter 5 - Part 2 81
Example: Recognize 1101 (continued)

 State transition arcs must represent the fact

that an input subsequence has occurred. Thus
we get:
0/0 1/0

1/0 1/0 0/0

A B C D

0/0 1/1
0/0
 Note that the 1 arc from state C to state C
implies that State C means two or more 1's have
occurred.
Chapter 5 - Part 2 82
 Formulation: Find State Table
 From the State Diagram, we can fill in the State Table.
 There are 4 states, one 0/0 1/0
input, and one output.
1/0 1/0 0/0
We will choose the form A B C D
with four rows, one for
each current state. 0/0 1/1

 From State A, the 0 and 0/0

1 input transitions have

Present Next State Output
been filled in along with State x=0 x=1 x=0 x=1
the outputs. A A B 0 0
B
C
D

Chapter 5 - Part 2 83
Formulation: Find State Table

 From the state diagram, we complete the

state table. 0/0 1/0

1/0 1/0 0/0

A B C D

0/0 1/1
0/0
Present Next State Output
State x=0 x=1 x=0 x=1
A A B 0 0
B A C 0 0
C D C 0 0
D A B 0 1
 What would the state diagram and state table
look like for the Moore model?
Chapter 5 - Part 2 84
State Assignment
 Counting Order Assignment: A = 0 0, B = 0 1,
C = 1 0, D = 1 1
 The resulting coded state table:
Present Next State Output
State x = 0 x = 1 x = 0 x = 1

00 00 01 0 0
01 00 10 0 0
10 11 10 0 0
11 00 01 0 1

Chapter 5 - Part 2 85
 Flip Flop Input and Output Equations
• The State diagram specifies , 4 states , two input values , two out put values and
two D-FF are required to represent 4 states.
• FF Input equation are derived.
• Output Equation is derived.

Chapter 5 - Part 1 86
Simplified FF Equations

 Simplified Equations are

Chapter 5 - Part 1 87
Sequential Circuit

Y1
D

C
R
Z

Y2
X D

Clock C
R
Reset

Chapter 5 - Part 1 88