SYSTEM DESIGN

USING
VISUAL INFORMATION
HIDING
Presented By:
Aniket Saha
Archan Sengupta Deep
Banerjee
Debapriya Basu Roy
Mentor:-Mr. Abhisek Basu
RCCIIT
Intellectual Property:

Intellectual property (IP) is a term referring to a

number of distinct types of creations of the mind
for which property rights are recognized. Unlike
any physical property which has definite physical
occupancy, intellectual property is actually a form
of creative piece of work.
 CLASSIFICATION
OF
INTELLECTUAL PROPERTIES

Based on its characterization, intellectual properties are

classified into three types:

a) Behavioral description (soft IP)

b) Structural description (firm IP)

c) Physical description (hard IP)

 COPYRIGHT PROTECTION
OF
INTELLECTUAL PROPERTIES
The goal of IP protection as a whole is to provide necessary
technologies to make enforcement a more manageable task
while deterring infringement at all levels of a design.

Fundamental requirements for a watermark are that it be

(1) transparent, i.e. not interfering with the design functionality

(2) robust, i.e. hard to remove or forge

(3) detectable, i.e. easy to extract from the design.

USE OF WATERMARKING STATES
IN
THE STATE MACHINE
Features of watermarking stream

1. The watermark assumes the form of a extraneous bit stream, hidden

inside states of FSMs.

2. The watermark is stored in some of the unused states of the FSMs. Each
unused state is responsible for producing a unique output.

3. This design is done in such a manner to avoid any impact on the

original functionality.

DISCRETE OTHER
STATES WATERMARK
ED STATE
 INFORMATION IS HIDING
BUT
WHERE?
The term information hiding here means hiding of the manufacturer
information from the user.

The system will move into watermarked states(having unique output)

after giving a special irrespective of the present state of the system.

Actually this unique permanent output determines the identity of the

manufacturer and is hidden.

W1/1001
A small part of a
watermarking
W2/1010 scheme

W3/1011
 A SIMPLE STATE MACHINE
DESIGN WITHOUT WATERMARK
STATE TRANSITION TABLE:
Present Next state Output
state INPUT(DEF) (Z2Z1Z0)

00 00 01 01 10 10 110
0 1 0 1 0 1
P P Q R S T U V 000
Q Q P R S T U V 001
R R P Q S T U V 010
S S P Q R T U V 011
T T P Q R S U V 100
U U P Q R S T V 101
V V P Q R S T U 110
STATE ASSIGNMENT TABLE:
Present Next state(ABC) Output
state INPUT(def)
000 001 010 011 100 101 110

a b c ABC ABC ABC ABC ABC ABC ABC Z Z Z

2 1 0

P 0 0 0 000 001 010 011 100 101 110 0 0 0

Q 0 0 1 001 000 010 011 100 101 110 0 0 1
R 0 1 0 010 000 001 011 100 101 110 0 1 0
S 0 1 1 011 000 001 010 100 101 110 0 1 1
T 1 0 0 100 000 001 010 011 101 110 1 0 0
U 1 0 1 101 000 001 010 011 100 110 1 0 1
V 1 1 0 110 000 001 010 011 100 101 1 1 0
 DESIGN EQUATION OF THE FSM WITHOUT
WATERMARKING

STATE EQUATIONS:

A=|a*d*|e+|a*d*|f+|c*d*|e*f+|b*d*|e*f+|c*d*e*|f+|b*d*e*|f+a*|b*|
d*|e*|f+a*|c*|d*|e*|f

B=a*|b*d*|f+|a*d*e*|f+|c*|d*e*f+|a*|d*e*f+|b*|d*e*f+|a*|b*|
d*e+a*b*|c*|e*|f+|a*b*|d*|e*|f

C=|a*d*|e*f+a*|b*|c*d*|e+a*b*|c*d*|f+a*|c*|d*e*|f+|a*b*|c*|d*e+|
a*|b*|d*e*f+|a*|b*|c*|d*f+a*|b*c*|e*|f+a*|b*c*|d*|f+|a*b*c*|d*|f+|
a*c*|d*|e*|f

OUTPUT EQUATIONS:

Z2=a;
Z1=b;
Z0=c;

 
A STATE MACHINE DESIGN WITH
WATERMARK
STATE TRANSITION TABLE:

FOR DISCRETE STATES:

Present state Next state Output
INPUT(DEF) (Z3Z2Z1Z0)
000 001 010 011 100 101 110 111

P P Q R S T U V W1 0000
Q Q P R S T U V W1 0001
R R P Q S T U V W1 0010
S S P Q R T U V W1 0011
T T P Q R S U V W1 0100
U U P Q R S T V W1 0101
V V P Q R S T U W1 0110

FOR WATERMARKED STATES:

Present State Next state(does not Output
depend upon inputs) (Z3Z2Z1Z0)
W1 W2 0111
W2 W3 1000
W3 W4 1001
W4 W5 1010
W5 W6 1011
W6 W7 1100
W7 W8 1101
W8 W9 1110
W9 P 1111
STATE ASSIGNMENT TABLE:
Present state Next state(ABC) Output
INPUT(def)
000 001 010 011 100 101 110 111
g a b c GABC GABC GABC GABC GABC GABC GABC GABC Z3 Z2 Z1 Z0
P 0 0 0 0 0000 0001 0010 0011 0100 0101 0110 0111 0 0 0 0
Q 0 0 0 1 0001 0000 0010 0011 0100 0101 0110 0111 0 0 0 1
R 0 0 1 0 0010 0000 0001 0011 0100 0101 0110 0111 0 0 1 0
S 0 0 1 1 0011 0000 0001 0010 0100 0101 0110 0111 0 0 1 1
T 0 1 0 0 0100 0000 0001 0010 0011 0101 0110 0111 0 1 0 0
U 0 1 0 1 0101 0000 0001 0010 0011 0100 0110 0111 0 1 0 1
V 0 1 1 0 0110 0000 0001 0010 0011 0100 0101 0111 0 1 1 0

WATERMARKED STATE:
Present Watermarked Next OUTPUT
State Watermarked
State(indepen
dent of input
DEF)
g a b c Y3Y 2 Y1 Y0 Z3 Z2 Z1 Z0
W1 0 1 1 1 1000 0 1 1 1
W2 1 0 0 0 1001 1 0 0 0
W3 1 0 0 1 1010 1 0 0 1
W4 1 0 1 0 1011 1 0 1 0
W5 1 0 1 1 1100 1 0 1 1
W6 1 1 0 0 1101 1 1 0 0
W7 1 1 0 1 1110 1 1 0 1
W8 1 1 1 0 1111 1 1 1 0
W9 1 1 1 1 0000 1 1 1 1
 DESIGN EQUATION OF THE FSM WITH
WATERMARKING

STATE EQUATIONS:

A=|a*d+|c*d*f+|b*d*f+|c*d*e+|b*d*e+a*|b*|d*|e*|f+a*|c*|d*|e*|f

B=|a*d*e+|c*e*f+|b*e*f+|a*e*f+|a*|b*e+a*|b*d*|f+a*b*|c*|e*|f+|
a*b*|d*|e*|f

C=|a*d*f+|b*d*e*f+|a*|b*e*f+|a*|b*|c*f+a*|b*|c*d*|e+a*b*|c*d*|
f+a*b*|c*d*e+a*|c*|d*e*|f+|a*b*|c*|d*e+a*|b*c*|e*|f+a*|b*c*|d*|
f+|a*b*c*|d*|f+|a*c*|d*|e*|f

WATERMARKED STATE EQUATIONS:

Y3=ga’+gc’+gb’+g’abc

Y2=gac’+gab’+ga’bc

Y1=gb’c+gbc’
OUTPUT EQUATIONS:

Z3=g;
Z2=a;
Z1=b;
Z0=c;

Thus we have designed the circuit equations or

design equations for both the FSMs, one without
watermarking and another with watermarking.
 PRESENT STATUS
WORKS DONE:
Understanding of the problem.
Design of FSM with no watermarking.
Design of FSM with watermarking.
Design of Corresponding state tables.

FUTURE WORK TO BE DONE

 Circuit design of the FSMs.

 Design of the FSMs using VHDL.
 Implementing those design on FPGA.
 CONCLUSION

Digital media piracy is one of the biggest problem that we are facing
now. Here we are addressing a specific problem of digital media
piracy i.e. copyright violation in intellectual property. We are looking
to find an effective method which will solve this problem in an
optimized manner. The method we are presenting here does not
interfere with the functionability of the FSMs, hence it is more
effective.
 ACKNOWLEDGEMENT

We like to express our deepest gratitude and thankfulness to Mr. Avishek

Basu (our beloved mentor and guide) and all the teachers of the
Electronics and Communication Engineering department of RCCIIT.

BIBLIOGRAPHY
1. www.wikipedia.com

2. Watermarking Techniques for Electronic Circuit Design

Edoardo Charbon and Ilhami Torunoglu

3. Fragile IP Watermarking Techniques

Amr T. Abdel-Hamid and Sofi`ene Tahar§