Digital Logic Design

Unit I: Logic Gates & Families

M. Sridhar
Associate Professor
Department of ECE
Logic Gates:
• The logic gate is the most basic building block of any digital system, including computers.

• There are three basic logic gates, namely the OR gate, the AND gate and the NOT gate. Other logic gates that

are derived from these basic gates are the NAND gate, the NOR gate, the EXCLUSIVEOR gate and the

EXCLUSIVE-NOR gate.
• The binary variables can have either of the two states, i.e. the logic ‘0’ state or the logic ‘1’ state. These logic

states in digital systems such as computers, for instance, are represented by two different voltage levels or two

different current levels.

• If the more positive of the two voltage or current levels represents a logic ‘1’ and the less positive of the two

levels represents a logic ‘0’, then the logic system is referred to as a positive logic system.
• If the more positive of the two voltage or current levels represents a logic ‘0’ and the less positive of the two

levels represents a logic ‘1’, then the logic system is referred to as a negative logic system.

Logic Gates & Families Department of ECE

OR gate:

• A logic gate used to perform the operation of logical addition is called an OR gate.

• The OR operation on two independent logic variables A and B is written as Y = A+B and reads
as Y equals A OR B.

AND gate:

• A logic gate used to perform logical multiplication is known as AND gate.

• The AND operation on two independent logic variables A and B is written as Y = A.B and
reads as Y equals A AND B.

Logic Gates & Families Department of ECE

NOT gate:

• A logic gate used to perform logical inversion is known as a NOT gate. If is the input to a
NOT circuit, then its output Y is given by Y = or and reads as Y equals NOT .

NAND gate:

• An AND gate followed by a NOT circuit makes it a NAND gate. The output of a NAND gate
is a logic ‘0’ when all its inputs are a logic ‘1’. For all other input combinations, the output is a
logic ‘1’.

Logic Gates & Families Department of ECE

 )

NOR gate:

• An OR gate followed by a NOT circuit makes it a NOR gate. The output of a NOR gate is a
logic ‘1’ when all its inputs are logic ‘0’. For all other input combinations, the output is a logic
‘0’.

EXCLUSIVE-OR gate:

• The output of an EX-OR gate is a logic ‘1’ when the inputs are unlike and a logic ‘0’ when the
inputs are like.

Logic Gates & Families Department of ECE

EXCLUSIVE-NOR gate:

• EXCLUSIVE-NOR (commonly written as EX-NOR) means NOT of EX-OR, i.e. the logic
gate that we get by complementing the output of an EX-OR gate.

• The output of a two-input EX-NOR gate is a logic ‘1’ when the inputs are like and a logic ‘0’
when they are unlike.

• NAND and NOR gates are known as Universal gates or Universal building blocks as they can
be used to implement any function.

Logic Gates & Families Department of ECE

Boolean Algebra:

• Boolean algebra is an algebraic structure defined on a set of elements B together with two binary operators
+ and · provided the following postulates are satisfied:

• a) Closure with respect to the operator +.

b) Closure with respect to the operator ·.

• a) An identity element with respect to +, designated by 0: x+0=0+x=x.

b) An identity element with respect to ·, designated by 1: x.1=1.x=x.

• a) Commutative with respect to +: x+y=y+x

b) Commutative with respect to ·: x.y=y.x

• a) · is distributive over +: x.(y+z)=x.y+x.z

b) + is distributive over ·: x+(y.z)=(x+y).(x+z)

• For every element, there exists an element x’(complement of ) such that x+x’=1 and x.x’=0.

Logic Gates & Families Department of ECE

Boolean Laws & Theorems:
Duality Principle:

It states that every algebraic expression deducible from the postulates of Boolean algebra
remains valid if the operators and identity elements are interchanged. If the dual of an
algebraic expression is desired, OR and AND operators are interchanged and 1’s are replaced
by 0’s and 0’s by 1’s.

• a) x+x’=1; x.x’=0

• b) x+x=x; x.x=x

• c) x+1=1; x.0=0

• d) DeMorgan’s Theorems: (x+y)’=x’.y’; (x.y)’=x’+y’

• e) x+xy=x

Logic Gates & Families Department of ECE

Universal Gates:
NOT gate:

AND gate:

OR gate:

EX-OR gate:

Logic Gates & Families Department of ECE

EX-NOR gate:

NAND gate:

NOR gate:

Logic Gates & Families Department of ECE

Boolean Expressions:

A Boolean expression or a function is an expression which consists of binary variables joined by the
Boolean connectives AND and OR along with NOT operation. Any Boolean expression can be
expressed in two forms:

– Canonical form

– Standard form

Canonical Form:

Sum of minterms: Any Boolean function can be expressed as a sum of minterms expression. A minterm
is a standard product which consists of all variables in either complemented or un-complemented
form for which the output is 1.
F  A' B' C  ABC' ABC

Product of maxterms: Any Boolean function can be expressed as a product of maxterms expression. A
maxterm is a standard sum which consists of all variables in either complemented or un-
F is0.( A  B  C )( A  B'C ' )
complemented form for which the output
Logic Gates & Families Department of ECE
Standard Form:

• Sum of Products (SOP): The sum of products is a Boolean expression containing AND terms,
called Product terms, of one or more literals each; the sum denotes the ORing of these terms.
F  A' B  BC  A' C
• Product of Sums (POS): It is a Boolean expression containing OR terms called Sum terms and
the product denotes the ANDing of these terms.

F  ( A  B )( B  C ' )( A  C ' )
Simplification using K-maps:

A Karnaugh map is a graphical representation of the logic system. It can be drawn directly from either
minterm (sum-of-products) or maxterm (product-of-sums) Boolean expressions. An n-variable
Karnaugh map has 2n squares, and each possible input is allotted a square. In the case of a minterm
Karnaugh map, ‘1’ is placed in all those squares for which the output is ‘1’, and ‘0’ is placed in all
those squares for which the output is ‘0’. 0s are omitted for simplicity. An ‘X’ is placed in squares
corresponding to ‘don’t care’ conditions.

Logic Gates & Families Department of ECE

 Two-Variable K-Map

a
b 0 1
0

Logic Gates & Families Department of ECE

 Three-Variable K-Map

ab
c 00 01 11 10

0 m0 m2 m6 m4

1 m1 m3 m7 m5

Logic Gates & Families Department of ECE

 Four-variable K-Map
ab
cd 00 01 11 10

00 m0 m4 m12 m8
01 m1 m5 m13 m9
11 m3 m7 m15 m11
10 m2 m6 m14 m10

Logic Gates & Families Department of ECE

• Use a K-Map to simplify the following Boolean
expression

F  a, b, c, d    m  0, 2,3, 6,8,12,13,15 

Logic Gates & Families Department of ECE

 ab
cd 00 01 11 10

00
1 1 1
01
1
11
1 1
10
1 1
F  abd  abc  acd  abd  acd
Logic Gates & Families Department of ECE
• Use a K-Map to simplify the following Boolean
expression

F  a, b, c, d    m  0, 2, 6,8,12,13,15 
 d  3,9,10 

Logic Gates & Families Department of ECE

 ab
cd 00 01 11 10

00
1 d 1 1
01
1 d
11
d 1
10
1 1
F  ac  ad  abd
Logic Gates & Families Department of ECE
• Simplify the following function

F   m(1,2,3,5,13)   d (6,7,8,9,11,15)

F  D  A' C

F  D  A' C

Logic Gates & Families Department of ECE

Two level Implementation:
• Any logic circuit can be implemented in two levels by representing the Boolean
function either in SOP or POS form. Two level NAND and NOR circuits can be
obtained by representing the expression in SOP and POS form respectively.

• Minimum propagation delay will be obtained by using two level implementation.

But as the number of terms increases, the number of inputs increases for the
second level gate.

NAND Implementation:
• By expressing the given function in SOP form, the logic circuit can be
implemented using two level NAND gates.

Logic Gates & Families Department of ECE

• Implement Y  A ( A ' B ' )  BC ' AC using NAND gates.

Y  AB' BC ' AC  AB' BC ' AC

Logic Gates & Families Department of ECE

NOR Implementation:
• By expressing the given function in POS form, the logic circuit can be
implemented using two level NOR gates.

• Implement Y  A' B  BC ' using NOR gates.

Y  B(A' B)(A'C' )(B  C' )

Logic Gates & Families Department of ECE

Multilevel Implementation:
• Multi level NAND or NOR implementation of a Boolean circuit can be
achieved by replacing each gate in the circuit with the NAND or NOR
equivalent circuits respectively. With this type of implementation, very large
propagation delay is achieved and only two input gates are required.

NAND Implementation:
• By replacing each gate in the circuit with the NAND equivalent, multi level
NAND circuit is achieved. When two single input NAND gates (inverters) are
in series, they can be removed.

Logic Gates & Families Department of ECE

• Implement the Boolean function Y  A( B  CD)  BC' using multi level
NAND gates.

Logic Gates & Families Department of ECE

NOR Implementation:
• By replacing each gate in the circuit with the NOR equivalent, multi level NOR
circuit is achieved. When two single input NOR gates (inverters) are in series,
they can be removed.

• Implement the Boolean function Y  A( B  CD)  BC' using multi level

NOR gates.

Logic Gates & Families Department of ECE

Logic Families:
• There are a variety of circuit configurations or more appropriately various
approaches used to produce different types of digital integrated circuit. Each
such fundamental approach is called a logic family.

• Bipolar Logic Families:

– Saturated: RTL, DCTL,HTL,IIL, DTL, TTL
– Non-saturated: Schottky TTL, ECL
• Unipolar Logic Families:
– PMOS
– NMOS
– CMOS

Logic Gates & Families Department of ECE

Characteristics of Logic families:
• Fanout: The fan-out of a gate specifies the number of standard loads that can be
connected to the output of the gate without degrading its normal operation.

• Power Dissipation: The power dissipation is a parameter expressed in milliwatts (mW)

and represents the amount of power needed by the gate. The amount of power that is
dissipated in a gate is calculated from the supply voltage and the current that is drawn
by the circuit.

• Propagation Delay: The propagation delay of a gate is the average transition delay time for

the signal to propagate from input to output when the binary signal changes in value. The
signals through a gate take a certain amount of time to propagate from the inputs to the
output. This interval of time is defined as the propagation delay of the gate and is
expressed in nanoseconds (ns).

Logic Gates & Families Department of ECE

 Noise Margin:

• Noise Margin: Noise margin is the maximum noise voltage added to an input
signal of a digital circuit that does not cause an undesirable change in the
circuit output. It is expressed in volts and represents the maximum noise signal
that can be tolerated by the gate.

• Speed–power product: A useful figure-of-merit used to evaluate different

logic families is the speed–power product, expressed in picojoules, which is the
product of the propagation delay (measured in nanoseconds) and the power
dissipation per gate (measured in milliwatts).

Logic Gates & Families Department of ECE

RTL Circuit: The basic circuit of the RTL logic family is the NOR gate. Each
input is associated with one resistor and one transistor.

• When any one of the input is high, the corresponding transistor is in saturation
and hence the output is low regardless of the states of the other transistors. If all
the inputs are low, the transistors are in cutoff and hence the output rises to V cc .

Logic Gates & Families Department of ECE

DTL Circuit: The basic circuit in the DTL digital logic family is the NAND gate
where each input is associated with one diode.

• When any one of the input is LOW, the diode corresponding to that input is in
conducting state and hence, the transistor is in OFF state and the output is
HIGH. With all the inputs HIGH, the transistor is in saturation and hence the
output is LOW.

Logic Gates & Families Department of ECE

Transistor-Transistor Logic (TTL): The NAND gate is the basic building
block of this logic family.

Standard TTL NAND gate Open – collector output gate

Logic Gates & Families Department of ECE

Totem pole output Three State gate

Logic Gates & Families Department of ECE

Emitter Coupled Logic (ECL): Emitter-coupled logic (ECL) is a non saturated digital
logic family and the basic gate is OR/NOR gate. Since transistors do not saturate, it is
possible to achieve propagation delays of 2 ns and even below 1 ns. This logic family
has the lowest propagation delay of any family and is used mostly in systems requiring
very high speed operation.

Logic Gates & Families Department of ECE

Integrated Injection Logic (IIL or I2L): Integrated Injection logic or current
injection logic is the newest of the logic families, which is finding widespread
use in LSI and VLSI circuits.
Inverter NAND gate

Logic Gates & Families Department of ECE

• The IIL logic gates are constructed using bipolar transistors only. The absence
of resistors makes it possible to integrate a large number of gates on a single
package.
NOR gate

Logic Gates & Families Department of ECE

MOS logic family:

Logic Gates & Families Department of ECE

Complementary MOS (CMOS) Logic family: CMOS device uses both n and p
transistors for operation and at any time only one device will be in conducting state
and thus reduces power dissipation.

Logic Gates & Families Department of ECE

 Comparison of Logic families:
Power Dissipation Propagation
Logic Family Fan-out Noise Margin (V)
(mW) Delay(ns)

Standard TTL 10 0.4 10 10

Schottky TTL 10 0.4 22 3

Low-power Schottky
20 0.4 2 10
TTL

ECL 25 0.2 25 2

IIL 8 0.35 0.1 1

CMOS 50 3 0.1 25

Logic Gates & Families Department of ECE