DK1 Power Presentation

BC466

SC1U10V5KX

2
1
SC1476_AGND R510
R123 1R3F
10R3

5
U29

2
D
PH5330
4 G

23
38
U67

3
S
BC102 1476_VCCA 30 2 1476_DH1
SC1476_AGND SC1U10V5KX VCCA TG1 1 1476_LX1
DRN1

V5_1

BST1
37 1476_DL1

CORE
4 BG1 36
16 DPRSLPVR DPRSL PGND1
SC1476_AGND

1
2
3
35 34 1476_ISH1 1 2
29,33,34,38 RUNPWROK EN ISH1 R486 10KR3F
16 33 1476_CL1 1 2
34 VCORE_PWRGD PWRGD CL1 R485 825R3F
H_VID5 9 32 1476_CMP1 1 2
4 H_VID[5:0] VID5 CMP1
10 R484 499R3F *SD
1

H_VID4
11 VID4 31 1 2
H_VID3 1476_CLRF
R152 12 VID3 CLRF S.B. R483 845R3F
H_VID2
100KR3 13 VID2 29 1 2
H_VID1 1476_CMPRF
VID1 CMPRF
14 R457 432R3F *SD
2

H_VID0
VID0 28 1 2
1476_CMP2
CMP2
VCORE_PWRGD 1476_CLSET 7
CLSET
R456 499R3F *SD
1476_HYS 8 27 1476_CL2 1 2
HYS CL2 R455 825R3F
26 1 2
1

1476_ISH2
C225 R183 ISH2 R454 10KR3F
SCD1U16V3KX R181 R151 16K5R3F 24 1476_DAC 1 2
61K9R3F 30K1R3F Proto-1B DAC R150 619R3F PWR_SRC
2

1476_PBOOT 6 18 1476_DH2
PBOOT TG2 19
Vboot=1.2V DRN2
1476_LX2
1476_VDRP 5 21 BC101
1

Vdpr=0.749V 1476_DL2
R184 15 VDPR BG2 22 SC1000P50V3KX
SS V5_2 PGND2
BST2
GND
SC1476_AGND 15KR3F
Proto-1B SC1476ITSTR
2

25
20
17

C224 SC1476_AGND
SCD01U16V2KX
S.B.
1

5
6
7
8
D
D
D
D
BC464 BC465 R182 R149 U69
SC1000P50V3KX 24K9R3F 1R3F
SC1000P50V3KX Proto-1B IRF7811A
2

BC463

G
BST2_VCORE

S
S
S
SC1476_AGND
SC1476_AGND SC1U10V5KX
1

D49

4
3
2
1
B0530W
2

• Revised : N50D00/Rock Lin

• Instructed : N50D10/Jim C Chen

1 Presentation Title
 DK1 Block
Diagram

2 Presentation Title
 Power on sequence block
diagram

 Please link to >>>>>>

Acrobat ¤å¥ó

3 Presentation Title
 Procedure Of Checking KBC
Pulses
1) Use probe to touch the CN11 pin 2 ( DEBUG_TXD )
without inserting AC adapter.
2) As for oscilloscope, set up Trigger Mode : Normal.
3) Final step that have to insert AC adapter but do
not press Power Button.
4) Eventually, we should have 4 set of pulses as
below.

4 Presentation Title
 Good Sign From
KBC

5 Presentation Title
 Procedure Of Checking KBC
Pulses
a) If we couldn't have such pulses from KBC.
b) Please go back to check the signal step by step.
ACAV_IN MAX1999_SHDN# 3D3V_S5
X1( PIN 1, 2, XTAL ) DEBUG_OUT.
c) There are several circuit portion listed below.

6 Presentation Title
 Procedure Of Checking KBC
Pulses

7 Presentation Title
 Procedure Of Checking KBC
Pulses

U55

8 Presentation Title
 Procedure Of Checking KBC
Pulses

9 Presentation Title
 Procedure Of Checking KBC
Pulses

10 Presentation Title
 Procedure Of Checking No Power
Issues
• Symptom : 3 LED light turn on entirely (FPC)

First Case:
a) Firstly, you can jump to check VCC_CORE_S0 power
plane.
b) Does CPU power comes up?
c) If doesn't . Please go back to check with the
power sequence from beginning as 5V_S3/+3VSRC
SUSPWROK 1D8V_S3/1D5V_S3 RUN_ON_D
1D05V_S0 VCC_CORE_S0 .
d) These action will check which power plane have no
power up.
e) The more detailed power sequence waveform have
attached
from page 12 to page 21.

11 Presentation Title
 Procedure Of Checking No Power
Issues
Second Case:
a) Assumed that CPU voltage can attain 0.9 Volt above.
b) We may prove that the rest of power plane before
VCC_CORE_S0 power plane would be fine.
c) Afterward, please check with ICH_PCIRST#
H_CPURST# . ( See fig.1, fig.2 below )
d) If ICH_PCIRST# still can’t exist, we can check the
following signal : RESET_OUT#( From KBC)
VRM_PWRGD.
e) If H_CPURST# can’t driven high, the following action
should
take is checking the GMCH_PWROK( R431 pin 2 ).
f) In addition, we can check whether reference voltage (2/3
VCCP) for GMCH correct or not, that is, GTLREF, H_VREF.
( R38 pin 1, GTLREF ), ( R311 pin 1, H_VREF ).

12 Presentation Title
 Fig.1 ( H_PWRGD,
ICH_PCIRST# )

13 Presentation Title
 Fig.2 ( H_CPURST#, ICH_PCIRST# )

14 Presentation Title
 Procedure Of Checking No Power Issues

1) If both H_PWRGD and H_CPURST# driven

high as fig.1, fig.2. We’ll keep tracking the
next signal which connect between CPU and
GMCH, that is, H_ADS#. ( Fig.3 ).
2) We can assume that CPU may failure if we
can’t
get these pulses in Fig.3.
3) Another case is only show up one pulse in
Fig.3
that we can suspect the failure in U40
( Bios Rom ).

15 Presentation Title
 Fig.3 ( H_ADS# )
H_ADS# is the “first signal” generated by CPU ,
18 GTL_ADS# CPU to NB Test pad only .

16 Presentation Title
 LPC_LFRAME# WAVEFORM COME OUT AFTER
H_ADS# PRODUCED BY CPU ( REFER TO PAGE 20 )

17 Presentation Title
 By the way, If above signal OK. Then we can check the
rest of CLK waveforms.

1) Check U62 ( clock GEN ) RN45, RN46 pin 3, 4

CPU CLK ( 100/133 MHz ).

18 Presentation Title
 2) Check memory CLK ( 200/266 MHz ) which asserts
from GMCH. Practically, we can probe the DDR socket (
normal type ) at pin 35, 37.

19 Presentation Title
 CPU access BIOS data
flow

VCC Clock VCC Clock VCC Clock VCC Clock

H_ADS# DMI_RXP/N LPC_LFRAME#

CPU N/B S/B BIOS
H_TRDY# DMI_TXP/N LPC_LAD(3:0)

H_CPURST# Reset Reset

H_D#(63:0)

20 Presentation Title
 DK1 POWER SEQUENCE WAVEFORM
Test Purpose: To record the timing sequence for the power rails.
Overview of Procedure: Measure the timing of the power rails. The definition of these timing
variables is given in the power sequencing document attached below this
Timing Variable Time table. Comments
T01 60.00 us Time of AD+ to DCBATOUT
T02 200.00 us Time of AD+ to ACAV_IN
T03 20.00 us Time of DCBATOUT to +3D3VRTC
T04 31.20 us Time of ACAV_IN to MAX1999_SHDN#
T05 2.18 ms Time of MAX1999_SHDN# to 3D3V_S5
T06 176.00 us Time of MAX1999_SHDN# to 5V_S5
T06-1 32.7ms Time of 3D3V_S5 to EC_RST#
T07 59.20 ms Time of SYS_PWRB# to +3V_SRC
T08 329.00 ms Time of SYS_PWRB# to AUX_EN#
T09 61.20 ms Time of SYS_PWRB# to SUS_ON
T10 380.00 us Time of SUS_ON to 5V_S3
T11 400.00 us Time of SUS_ON to 3VSUS_ON
T12 268.00 ms Time of SUS_ON to +15V
T13 2.58 ms Time of SUS_ON to ICH_RSMRST#
T14 1.40 ms Time of 3VSUS_ON to 3D3V_S3
T15 16.00 us Time of 5V_S3 to +15V
T16 1.51 ms Time of 5V_S3 to SUSPWROK_1999
T17 2.21 ms Time of 5V_S3 to ICH_RSMRST#
T18 820.00 us Time of SUSPWROK_1999 to 1D5V_S3
T19 2.98 ms Time of SUSPWROK_1999 to 1D8V_S3
T20 1.94 ms Time of 1D8V_S3 to DDR_VREF_S3
T21 98.00 ms Time of ICH_RSMRST# to ICH_SLP_S3#
T22 98.40 ms Time of ICH_RSMRST# to RUN_ON
T23 106.00 ms Time of ICH_RSMRST# to RUN_PWROK
T24 1.08 us Time of ICH_SLP_S3# to PM_PWRBTN#
T25 752.00 us Time of ICH_SLP_S3# to 5V_S0
T26 248.00 us Time of ICH_SLP_S3# to 1D5V_S0
T27 2.02 ms Time of ICH_SLP_S3# to RUN_ON_D
T28 400 us Time of RUN_ON_D to 3D3V_S0
T29 576.00 us Time of RUN_ON_D to 2D5V_S0
T30 1.21 ms Time of RUN_ON_D to 1D05V_S0
T31 6.52 ms Time of RUN_ON_D to RUN_PWROK
T32 6.14 ms Time of 3D3V_S0 to RUN_PWROK
T33 1.78 ms Time of RUN_PWROK to VCC_CORE_S0
T34 140.00 us Time of VCC_CORE_S0 to CLK_PWRGD#
T35 4.54 ms Time of VCC_CORE_S0 to VRM_PWRGD
T36 -7.60 ms Time of VCC_CORE_S0 to RESET_OUT#
T37 4.42 ms Time of CLK_PWRGD# to VRM_PWRGD
T38 145.00 ms Time of RESET_OUT# to ICH6_PWROK
T39 1.04 ms Time of ICH6_PWROK to ICH_PCIRST#
T40 992.00 us Time of ICH_PCIRST# to H_CPURST#
Section Owner: Jim C Chen
Section Tester: Abel Chang
Time To Complete: 06/15
Date Finished: 06/15

21 Presentation Title