Array Structured Memories: Stmicro/Intel Ucsd Cad Lab Weste Text

Array Structured Memories
STMicro/Intel
UCSD CAD LAB
Weste Text
1
STMicro/Intel/UCSD/THNU
EE141 Memory
Memory Arrays
Memory Arrays
Random Access Memory Serial Access Memory Content Addressable Memory

(CAM)
Read/Write Memory Read Only Memory

Shift Registers Queues
(RAM) (ROM)
(Volatile) (Nonvolatile)
Serial In Parallel In First In Last In

Static RAM Dynamic RAM Parallel Out Serial Out First Out First Out
(SRAM) (DRAM) (SIPO) (PISO) (FIFO) (LIFO)
Mask ROM Programmable Erasable Electrically Flash ROM

ROM Programmable Erasable
(PROM) ROM Programmable
(EPROM) ROM
(EEPROM)
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EE141 Memory
Feature Comparison Between
Memory Types
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EE141 Memory
Array Architecture
 2n words of 2m bits each
 If n >> m, fold by 2k into fewer rows of more columns
bitline conditioning
wordlines
bitlines
row decoder
memory cells:
2n-k rows x
2m+k columns
n-k
k column
circuitry
n column
decoder
2m bits
 Good regularity – easy to design

 Very high density if good cells are used
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EE141 Memory
Memory - Real Organization Array of N x K words
------------- columns ------------ KxM
S0
C of M bit words row 0
------------- rows R------------


Log2R Row
Address Decoder
Lines
C of M bit words row N-2
C of M bit words row N-1

SR-1
- - - - KxM bits - - - -
Log2C
Address Column Select
Lines
M bit data word
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EE141 Memory
Hierarchical Memory Architecture
Row
Address
Column
Address
Block
Address
Global Data Bus

Control Block Selector Global
Circuitry Amplifier/Driver
I/O
Advantages:
1. Shorter wires within blocks
2. Block address activates only 1 block => power savings
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EE141 Memory
Array Organization Design Issues
 aspect ratio should be relative square
 Row / Column organisation (matrix)
 R = log2(N_rows); C = log2(N_columns)
 R + C = N (N_address_bits)
 number of rows should be power of 2
 number of bits in a row need not be…
 sense amplifiers to speed voltage swing
 1 -> 2R row decoder
 1 -> 2C column decoder
 M column decoders (M bits, one per bit)
– M = output word width
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EE141 Memory
Simple 4x4 SRAM Memory
read
precharge bit line precharge
enable
WL[0]
BL !BL
Row Decoder
2 bit width: M=2 A1
WL[1]
R = 2 => N_rows = 2R = 4
C=1 A2 WL[2]
N_columns = 2c x M = 4
N=R+C=3 WL[3]
Array size =
N_rows x N_columns = 16
A0
Column Decoder
A0!
clocking and
control -> sense amplifiers
WE! , OE! write circuitry
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EE141 Memory
SRAM Read Timing (typical)
 tAA (access time for address): time for stable
output after a change in address.
 tACS (access time for chip select): time for stable
output after CS is asserted.
 tOE (output enable time): time for low impedance
when OE and CS are both asserted.
 tOZ (output-disable time): time to high-impedance
state when OE or CS are negated.
 tOH (output-hold time): time data remains valid
after a change to the address inputs.
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EE141 Memory
SRAM Read Timing (typical)
ADDR stable stable stable
 tAA Max(tAA, tACS)
CS_L
tOH
tACS
OE_L
tAA tOZ tOE tOZ tOE
DOUT valid valid valid
WE_L = HIGH
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EE141 Memory
SRAM Architecture and Read
Timings
tOH
tAA
tACS
tOZ
tOE
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EE141 Memory
SRAM write cycle timing
~WE controlled
~CS controlled
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EE141 Memory
SRAM Architecture and Write
Timings
tDH
Setup time = tDW
Write
driver
tWP-tDW
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EE141 Memory
SRAM Cell Design
 Memory arrays are large
 Need to optimize cell design for area and
performance
 Peripheral circuits can be complex
– 60-80% area in array, 20-40% in periphery
 Classical Memory cell design
 6T cell full CMOS
 4T cell with high resistance poly load
 TFT load cell
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EE141 Memory
Anatomy of the SRAM Cell
Write:
•set bit lines to new data value Read:
•b’ = ~b •set bit lines high
•raise word line to “high” •set word line high
•sets cell to new state •see which bit line goes
•Low impedance bit-lines low
•High impedance bit lines
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EE141 Memory
SRAM Cell Operating Principle
•Inverter Amplifies
•Negative gain
•Slope < –1 in middle
•Saturates at ends
• Inverter Pair Amplifies
•Positive gain
•Slope > 1 in middle
•Saturates at ends
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EE141 Memory
Bistable Element
Stability
Require Vin = V2
Stable at endpoints
recover from pertubation
Metastable in middle
Fall out when perturbed
Ball on Ramp Analogy

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EE141 Memory
Cell Static Noise Margin
Cell state may be disturbed by
•DC
•Layout pattern offset
•Process mismatches
•non-uniformity of implantation
•gate pattern size errors
•AC
•Alpha particles
•Crosstalk SNM (static noise margin)
•Voltage supply ripple = Maximum Value of Vn
•Thermal noise
not flipping cell state
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EE141 Memory
SNM: Butterfly Curves
1
SNM
2
SNM
1
2 1 1 2
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EE141 Memory
SNM for Poly Load Cell
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EE141 Memory
12T SRAM Cell
bit
write
 Basic building block: write_b
SRAM Cell read

 1-bit/cell (noise margin
again) read_b
 12-transistor (12T)
SRAM cell
 Latch with TM-gate write
 Separately buffered read
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EE141 Memory
6T SRAM Cell
 Cell size accounts for most of array size
 Reduce cell size at cost of complexity/margins
 6T SRAM Cell
 Read:
 Precharge bit, bit_b bit bit_b
word
 Raise wordline
 Write:
 Drive data onto bit, bit_b
 Raise wordline
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EE141 Memory
SRAM Design
TI 65nm: IBM 65nm: Intel 65nm:

0.46x1.06um2 0.41x1.25um2 0.46x1.24um2
* Figures courtesy A. Chatterjee et al., P. Bai et al., and Z. Luo et al.,

Int. Electron Device Meeting Tech. Digest, 2004
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EE141 Memory
Vertical 6T Cell Layout B- B+ N Well
Connection
VDD
PMOS
Pull Up
Q/ Q
NMOS
Pull Down
GND
SEL
SEL MOSFET
Substrate
Connection
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EE141 Memory
SRAM Bitcell Design
WL VSS VDD BL
VDD PG1 PU2 PD2

PU1 PU2
NL NL NR NR WL
NL WL
PG1
NR PG2 PD1 PU1 PG2
PD2
PD1
VSS
BLB BL BLB VDD VSS
Schematic Layout Micrograph
 Requirements of SRAM bitcell design
 Stable read operation: Do not disturb data when reading
 Stable write operation: Must write data within a specified time
 Stable data retention: Data should not be lost
 Typical transistor sizing
 Cell ratio (= I(PD) / I(PG)) = 1.5 ~ 2.5
 Pull-up ratio (= I(PU) / I(PG)) = 0.5
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EE141 Memory
Detailed SRAM Bitcell Layout
– Vertical: 2 poly pitch

– Horizontal: 5 contact pitch
– Poly-to-contact space > overlay + spacer + strain_layer + CD_control
(6.4nm*) ( 8nm**) (10nm**) ( 2.6nm*) = 27nm
– 1 poly pitch = 2 poly_to_contact + poly_width + contact_width
 54 + 32 + 45** = 131 nm
A pitch is a multiple of a drawing grid for fine-grain pattern placement
Ex.: 5 grid per pitch  drawing grid = (131/5) = 26 nm
poly CNT
Ex.: 6 grid per pitch  drawing grid = (131/6)
* From ITRS= 22 nm
32nm tech.
spacer ** From S. Verhaegen et al.,
SPIE Adv. Litho., 2008
Strain layer
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EE141 Memory
SRAM Read
bit bit_b
 Precharge both bitlines high word
P1 P2
 Then turn on wordline N2 N4
 One of the two bitlines will A A_b
N1 N3
 be pulled down by the cell
 Ex: A = 0, A_b = 1 A_b bit_b
 bit discharges, bit_b stays high 1.5
 But A bumps up slightly

1.0
bit
 Read stability word
0.5
 A must not flip A
 N1 >> N2 0.0
0 100 200 300 400 500 600
time (ps)
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EE141 Memory
bit bit_b
word
P1 P2
N2 N4
A A_b
N1 N3
SRAM Read, 0 is stored in the cell

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EE141 Memory
bit bit_b
SRAM Write word
N2
P1 P2
N4
 Drive one bitline high, other low A A_b
N1 N3
 Then turn on wordline
 Bitlines overpower cell
 Ex: A = 0, A_b = 1, bit = 1, bit_b = 0
 Force A_b low, then A rises high
 Writability A_b
 Must overpower feedback A

1.5
 P2 << N4 to force A_b low, bit_b

1.0
 N1 turns off, P1 turns on,
 raise A high as desired 0.5
word
0.0
0 100 200 300 400 500 600 700
time (ps)
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EE141 Memory
SRAM Sizing
 High bitlines must not overpower
inverters during reads
 But low bitlines must write new value
into cell bit bit_b
word
weak
med med
A A_b
strong
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EE141 Memory
SRAM Column Example
read write Bitline Conditioning
2
More
Cells
word_q1
bit_b_v1f
bit_v1f
SRAM Cell
write_q1
data_s1
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EE141 Memory
Decoders
 n:2n decoder consists of 2n n-input AND gates
 One needed for each row of memory
 Build AND from NAND or NOR gate
choose minimum size to reduce
load on the address lines
A1 A0
A1 A0
1/2 4 16
1 1 8 word
word
A0 A1 2 8
A1 1 4 1 1
A0 1
word0 word0
word1 word1
Pseudo-nMOS
word2
static word2
word3
word3
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EE141 Memory
Single Pass-Gate Mux
A1 A0
B0 B1 B2 B3
bitlines propagate
through 1 transistor
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EE141 Memory
Decoder Layout
 Decoders must be pitch-matched to
SRAM cell
 Requires very skinny gates
A3 A3 A2 A2 A1 A1 A0 A0
VDD
word
GND
NAND gate buffer inverter
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EE141 Memory
Large Decoders
 For n > 4, NAND gates become slow
 Break large gates into multiple smaller gates
A3 A2 A1 A0
word0
word1
word2
word3
word15
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EE141 Memory
Predecoding
 Many of these gates are redundant
 Factor out common A3
gates into predecoder

A2
A1
 Saves area A0
 Same path effort predecoders
1 of 4 hot
predecoded lines
word0
word1
word2
word3
word15
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EE141 Memory
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EE141 Memory
Column Circuitry
 Some circuitry is required for each
column
 Bitline conditioning
 Sense amplifiers
 Column multiplexing
 Each column must have write drivers
and read sensing circuits
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EE141 Memory
Column Multiplexing
 Recall that array may be folded for good
aspect ratio
 Ex: 2k word x 16 folded into 256 rows x
128 columns
 Must select 16 output bits from the 128
columns
 Requires 16 8:1 column multiplexers
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EE141 Memory
Typical Column Access
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EE141 Memory
Pass Transistor Based Column
Decoder
BL !BL BL !BL BL !BL 3 3 2 2 1 1 BL0 !BL0
2 input NOR decoder
S3
A1
S2
S1
A0
S0
Data !Data
 Advantage: speed since there is only one extra

transistor in the signal path
 Disadvantage: large transistor count
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EE141 Memory
Tree Decoder Mux
 Column MUX can use pass transistors
 Use nMOS only, precharge outputs
 One design is to use k series transistors for 2k:1 mux
 No external decoder logic needed
B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7
A0
A0
A1
A1
A2
A2
Y Y
to sense amps and write circuits
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EE141 Memory
Ex: 2-way Muxed SRAM
2
More More
Cells Cells
word_q1
2-to-1 mux
A0
A0
write0_q1 2 two bits from

write1_q1
two cells and
data_v1 selected by A0
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EE141 Memory
Bitline Conditioning
 Precharge bitlines high before reads
 
bit bit_b
bit bit_b
 Equalize bitlines to minimize voltage

difference when using sense amplifiers
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EE141 Memory
Sense Amplifier: Why? Cell pull
down
 Bit line cap significant for large array Xtor
 If each cell contributes 2fF, resistance
– for 256 cells, 512fF plus wire cap RCV


 Pull-down resistance is about 15K Vdd
 RC = 7.5ns! (assuming V = Vdd)
 Cannot easily change R, C, or Vdd, but can change
Cell current
V i.e. smallest sensed voltage
 Can reliably sense V as small as <50mV
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EE141 Memory
Sense Amplifiers
 Bitlines have many cells attached
 Ex: 32-kbit SRAM has 256 rows x 128 cols
 128 cells on each bitline
 tpd  (C/I) V
 Even with shared diffusion contacts, 64C of
diffusion capacitance (big C)
 Discharged slowly through small transistors (small
I)
 Sense amplifiers are triggered on small voltage
swing (reduce V)
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EE141 Memory
Differential Pair Amp
 Differential
pair requires no clock
 But always dissipates static power
P1 P2
sense_b sense
bit N1 N2 bit_b
N3
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EE141 Memory
Clocked Sense Amp
 Clocked sense amp saves power
 Requires sense_clk after enough bitline swing
 Isolation transistors cut off large bitline capacitance
bit bit_b
sense_clk isolation
transistors
regenerative
feedback
sense sense_b
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EE141 Memory
Sense Amp Waveforms
1ns / div
bit
200mV
bit’
wordline wordline
begin precharging bit lines
BIT
2.5V
BIT’
sense clk sense clk

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EE141 Memory
Write Driver Circuits
50
EE141 Memory
Dual-Ported SRAM
 Simple dual-ported SRAM
 Two independent single-ended reads
 Or one differential write bit bit_b
wordA
wordB
wordA reads bit_b (complementary)
wordB reads bit (true)
 Do two reads and one write by time multiplexing

 Read during ph1, write during ph2
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EE141 Memory
Multiple Ports
 We have considered single-ported SRAM
 One read or one write on each cycle
 Multiported SRAM are needed for register files
 Examples:
 Multicycle MIPS must read two sources or write a
result on some cycles
 Pipelined MIPS must read two sources and write a
third result each cycle
 Superscalar MIPS must read and write many
sources and results each cycle
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EE141 Memory
Multi-Ported SRAM
 Adding more access transistors hurts read stability
 Multiported SRAM isolates reads from state node
 Single-ended design minimizes number of bitlines
bA bB bC bD bE bF bG
wordA
wordB
wordC
wordD
wordE
wordF
wordG
write
circuits
read
circuits
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EE141 Memory
Logical effort of RAMs
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EE141 Memory
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EE141 Memory
Twisted Bitlines
 Sense amplifiers also amplify noise
 Coupling noise is severe in modern processes
 Try to couple equally onto bit and bit_b
 Done by twisting bitlines
b0 b0_b b1 b1_b b2 b2_b b3 b3_b
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EE141 Memory
Alternative SRAM Cells
 Low Voltage/High Leakage/Process Variations crowd
the operating margins of conventional SRAM
 Alternative Sense Amplifiers, column and row
arrangements, adaptive timing, smaller hierarchy,
redundant and spare rows/columns have all been
addressed in the literature with some success.
 Some problems come from the cell design itself–
modifying the cell can break conflicting demands for
optimization
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EE141 Memory
10T
 Features
 BL Leakage reduction
 Approaches
 Separated Read port
 Stacked effect by M10
 Performance
 400mV@475kHz, 3.28uW
 320mV W/O Read error@27℃
 380mV W/O Write error@27℃
 Vmin=300mV@1% bit errors
 256 bits/BL
A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation

B. Calhoun & A. Chandrakasan, JSSC, 2007
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EE141 Memory
10T
 Features
 BL leakage reduction of data
 Approaches
 Virtual GND Replica
 Reverse Short Channel Effect
 BL Writeback
 Performance
 0.2V@100kHz, 2uW
 1024 bits/BL
 130nm process technology
A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and

Virtual Ground Replica Scheme
Chris Kim, ISSCC,
59
2007
EE141 Memory
10T
 Features
 ST cell array can work @160mV
 2.1x larger than 6T cell
 Approaches
 Schmitt Trigger based cell
 Good stability @ LowVDD
 Good scalability
 Performance
 Read SNM↑1.56x @VDD=0.4V
 More power saving
 Leakage power↓18%
 Dynamic power↓50%
 Hold SNM @150mV is 2.3x of 6T
 130nm process
A 160mV Robust Schmitt Trigger Based Subthreshold SRAM

K. Roy, JSSC, 2007
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EE141 Memory
9T
 Features
 Modifying from 10Tcell
 17% more area than 6T cell
 16.5% less area than 10T cell
 Approaches
 More leakage saving than 8T cell
 Separated read port
 Performance
 128 bits/BL @350mV ,100MHz
 Hold SNM=117mV @300mV
 Stand-by power: 6uW
 65nm process
A 100MHz to 1GHz, 0.35V to 1.5V Supply 256x64 SRAM Block using

Symmetrized 9T SRAM cell with controlled Read
S. A. Verkila,et al, Conference on VLSI Design, 2008
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EE141 Memory
9T
 Features
 Read stability enhancement
 Leakage power reduction
 Approaches
 Min. sizing of N3, N4 and negative
Vg7, and larger Node3 during
stand-by mode for leakage
reduction
 Performance
 2x R-SNM cf. 6T
 22.9% leakage power reduction
 65 nm PTM
High Read Stability and Low Leakage Cache Memory Cell

Z. Liu and V. Kursun, IEEE Conference, 2007
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EE141 Memory
8T
 Features
 No read disturb
 About 30% area penalty
 Approaches
 Separate Read & Write WL
 Performance
 Larger SNM than 6T
 Better scalability than 6T
Stable SRM Cell Design for the 32nm Node and Beyond
Leland Chang et. al,
Symp. on VLSI,2005
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EE141 Memory
8T
 Features
 No read disturb
 Low VDD(350mV)
 Low subthreshold(Sub. Vt) leakage
 Approaches
 Separate Read &Write WL
 Foot-drivers reduce the sub.Vt leakage
 Performance
 65nm process ,128 cells/row
 Operating @ 25KHz
 2.2uW leakage power
A 256kb 65nm 8T Subhreshold SRAM Employing Sense-Amplifier Redundancy

N. Verma ,and A. P. Chandrakasan, JSSC,2008
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EE141 Memory
7T
 Features
 23% smaller than Conv. 6T bitcell
 Low VDD(440mV)
 Not suit for low speed demand
 Approaches
 Separate Read &Write WL
 Seperate Read &Write BL
 Data protection nMOS:N5
 Performance
 20ns access time@0.5V
 90nm process
A Read-Static-Noise-Margin-Free SRAM Cell forLow-VDD and

High-Speed Applications NEC, JSSC, 2006
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EE141 Memory
7T
 Features
 90% power saving
 Approaches
 BL swing: VDD/6
 Performance
 0.35um proces
 Leakage not
controlled well
90% Write Power-Saving SRAM Using Sense-Amplifying Memory Cell

T. Sakurai et. al., JSSC, 2004
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EE141 Memory
7T
 Features
 Low write power
 SNM is effected by “Read pattern”
(Read 0-N2,P2,N4 & Read 1-
N1,P1,N3,N5)
 17.5% larger than 6T
 Approaches
 Reducing write power by cut off
the (feedback) connection to BL
 Performance
 0.18um proces
 49% write power saving
Novel 7T SRAM Cell For Low Power Cache Design

R. Aly, M. Faisal and A. Bayoumi
IEEE SoC Conf., 2005
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EE141 Memory
6T
• Features BL
– Single-ended
– Low VDD WL
• Approaches
– Adjustable header/footer (virVDD,
virGND)
• Performance
– VDD range: 1.2V~193mV
– Vmin=170mV with 2% redundancy WL
A Sub-200mV 6T SRAM in 0.13μm CMOS

EE141
ISSCC, 2007
68
Memory
5T
• Features
– Single-ended
– Single BL, Single WL
– Area 23% smaller than 6T
• Approaches
– BL precharge to Vpc=600mV
– Asymmetric cell sizing
– Differential SA is used for Read
• Performance
– 75% BL leakage reduction cf. 6T
– SNM is 50% lower than the 6T’s
– 0.18um process High-skewed Low-skewed
Inverter Inverter
A High Density, Low Leakage, 5T SRAM for Embeded Caches

I. Carlson et.al., ESSCIRC, 2004
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EE141 Memory
Example Electrical Design: UCSD 32nm
prototype
• Butterfly (read stability) • SPICE Model:
• N-curves (read and write stability) – 32nm HKMG (high-K/metal-
gate) from PTM
• Iread (read stability and access
• Reference Design
time) – Scaled bitcell from TSMC
• VDDHOLD (data retention) 90nm bitcell
• Ileakage (power and data retention)
32nm scaled from

32nm proposed
TSMC 90nm TSMC 90nm
(for 30x12, 25x12)
(REFERENCE)
L (nm) W (nm) L (nm) W (nm) L (nm) W (nm)
Pull-up 100 100 32 32 32 44
Pull-down 100 175 32 56 32 88
Pass-Gate 115 120 37 38 32 44
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EE141 Memory
Butterfly and N-Curves
• Measure method
– Increase VR and measure VL
– Increase VL and measure VR
– Make voltage transfer curve in VR
and VL axes  Butterfly
– Measure Iin  N-curve
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EE141 Memory
Iread, Ileakage and VDDHOLD
 Iread
 Measure bitline current when WL WL
switches to high VDD
 ILEAKAGE A1 A2
nr
‘1’ nl
 Measure VDD (or VSS) current when C1 ‘0’
C2
WL=0
B1 B2
 VDDHOLD
BLb BL
 Decreasing VDD voltage, while WL=0 ‘1’ ‘1’
 Measure minimum VDD voltage when
| V(nl) - V(nr) | = ‘sensing margin’
(100mV is assumed)
32nm proposed
REFERENCE
(for 30x12 and 25x12)
Iread 41.2 uA 66.7 uA
Ileakage 85.4 nA 142.7 nA
VDDHOLD 110 mV 118 mV
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EE141 Memory
Corner Simulation: Butterfly and N-Curve
• Three candidate
1.20E+00 1.20E+00 1.20E+00
layouts across operating

25x10, SS, 125degC
25x12, SS, 125degC
25x10,corners
NN, 25degC show little difference
25x10, FF, -40degC
1.00E+00 1.00E+00
25x12, NN, 25degC 1.00E+00
25x12, FF, -40degC
8.00E-01
30x12, SS, 125degC 8.00E-01 30x12, NN, 25degC 8.00E-01 30x12, FF, -40degC
6.00E-01 6.00E-01 6.00E-01
4.00E-01 4.00E-01 4.00E-01
2.00E-01 2.00E-01 2.00E-01
0.00E+00 0.00E+00 0.00E+00

0 0.2 0.4 0.6 0.8 1 1.2 0 0.2 0.4 0.6 0.8 1 1.2 0 0.2 0.4 0.6 0.8 1 1.2
1.0E-04 1.0E-04 1.0E-04
5.0E-05 5.0E-05
5.0E-05
0.0E+00 0.0E+00
1
6
1
6
11
16
21
26
31
36
41
46
51
56
61
66
71
76
81
86
91
96
11
16
21
26
31
36
41
46
51
56
61
66
71
76
81
86
91
96
101
101
0.0E+00
1
6
11
16
21
26
31
36
41
46
51
56
61
66
71
76
81
86
91
96
101
-5.0E-05 -5.0E-05
-5.0E-05 25x10 25x10 25x10
25x12 -1.0E-04 25x12 -1.0E-04 25x12
30x12 30x12 30x12
-1.0E-04 -1.5E-04 -1.5E-04
(SS, 125degC, 1.0V) (NN, 25degC, 1.0V) (FF, -40degC, 1.0V)

73
EE141 Memory
Corner Simulation: Iread , Ileakage and VDDHOLD
Iread (A) Ileakage (A)
1.80E-04 1.00E-04
1.60E-04 FF, -40 25x10 FF, -40 25x10
1.00E-05
1.40E-04 FF, -40 25x12 FF, -40 25x12
1.20E-04 FF, -40 30x12 1.00E-06 FF, -40 30x12
1.00E-04 NN, 25 25x10 NN, 25 25x10
1.00E-07 NN, 25 25x12
8.00E-05 NN, 25 25x12
NN, 25 30x12 NN, 25 30x12
6.00E-05 1.00E-08
SS, 125 25x10 SS, 125 25x10
4.00E-05
SS, 125 25x12 1.00E-09 SS, 125 25x12
2.00E-05 SS, 125 30x12 SS, 125 30x12
0.00E+00 1.00E-10
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 VDD (V)
0.13
0.128
0.126
0.124
VDDHOLD (V) 0.122
0.12
0.118
0.116
0.114
0.112
25x10 25x12 30x12 25x10 25x12 30x12 25x10 25x12 30x12
FF, -40 NN, 25 SS, 125
74
EE141 Memory

Array Structured Memories: Stmicro/Intel Ucsd Cad Lab Weste Text

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Array Structured Memories: Stmicro/Intel Ucsd Cad Lab Weste Text

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Array Structured Memories

Random Access Memory Serial Access Memory Content Addressable Memory

Read/Write Memory Read Only Memory

Serial In Parallel In First In Last In

Mask ROM Programmable Erasable Electrically Flash ROM

 Good regularity – easy to design

------------- rows R------------

C of M bit words row 2

C of M bit words row N-1

M bit data word

Global Data Bus

WE! , OE! write circuitry

 tAA Max(tAA, tACS)

tAA tOZ tOE tOZ tOE

DOUT valid valid valid

Ball on Ramp Analogy

 Basic building block: write_b

SRAM Cell read

TI 65nm: IBM 65nm: Intel 65nm:

* Figures courtesy A. Chatterjee et al., P. Bai et al., and Z. Luo et al.,

VDD PG1 PU2 PD2

– Vertical: 2 poly pitch

 bit discharges, bit_b stays high 1.5

 But A bumps up slightly

SRAM Read, 0 is stored in the cell

SRAM Write word

 Must overpower feedback A

 P2 << N4 to force A_b low, bit_b

NAND gate buffer inverter

gates into predecoder

 Same path effort predecoders

 Advantage: speed since there is only one extra

write0_q1 2 two bits from

 Equalize bitlines to minimize voltage

– for 256 cells, 512fF plus wire cap RCV

sense clk sense clk

 Do two reads and one write by time multiplexing

A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation

A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and

A 160mV Robust Schmitt Trigger Based Subthreshold SRAM

A 100MHz to 1GHz, 0.35V to 1.5V Supply 256x64 SRAM Block using

High Read Stability and Low Leakage Cache Memory Cell

A 256kb 65nm 8T Subhreshold SRAM Employing Sense-Amplifier Redundancy

A Read-Static-Noise-Margin-Free SRAM Cell forLow-VDD and

90% Write Power-Saving SRAM Using Sense-Amplifying Memory Cell

Novel 7T SRAM Cell For Low Power Cache Design

A Sub-200mV 6T SRAM in 0.13μm CMOS

A High Density, Low Leakage, 5T SRAM for Embeded Caches

32nm scaled from

layouts across operating

4.00E-01 4.00E-01 4.00E-01

2.00E-01 2.00E-01 2.00E-01

0.00E+00 0.00E+00 0.00E+00

1.0E-04 1.0E-04 1.0E-04

(SS, 125degC, 1.0V) (NN, 25degC, 1.0V) (FF, -40degC, 1.0V)

FF, -40 NN, 25 SS, 125

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