Question bank on FE part

• Define retiming transformation. What is the use of it in high level synthesis?

• Discuss steps involved in ROBDD from OBDD with an example
• Explain purpose of Gate Level Modeling and simulation.
• What do you know about Switch Level Modeling and Simulation
• What is Two-level Logic Synthesis and how it is used in FE design
• Explain how Hardware Allocation and Assignment is done.
• What is scheduling and explain any algorithm on scheduling
• Provide difference between static and dynamic timing analysis
• What are ways of reducing power ?
• What are different types of power analysis done in VLSI circuits
• What is DFT, DFD and how it is useful for testing SOCs
• What are techniques used in analog circuit testing on silicon
• what is BIST , Explain how it is used for testing
• Explain what is fault coverage , yield and DPM
• What is boundary scan and how it is used for testing
• Draw a random generator circuit and explain how it is useful in testing
• What are different testing hooks we provide during SOC design phase & explain
each of them briefly
• Explain classification of simulators in VLSI design and testing
• Explain your understanding about VHDL, RTL, behavioral model and logic synthesis
• What are Verification methods used at different levels of abstraction of design
• What all front end validation and design tools you know?
• Explain how clock design and timing validation is taken care at SOC level
• What power optimization and analysis is needed at every level of design?
• Explain in detailed static analysis method
• What do you accomplish with dynamic timing analysis
• Why hardware allocation and assignment is critical in high level
synthesis of design.
• How scheduling helps during design and simulation phase
• Explain hardware models for high level synthesis
• What are assumptions in combinational logic synthesis