Lecture 3:

Introduction
to CMOS
 About these Notes
 Lecture notes © 2011 David Money Harris
 Official website: http://
pages.hmc.edu/harris/cmosvlsi/4e/index.html

0: Introduction CMOS VLSI Design 4th Ed. 2

 Introduction
 In this lecture we will be covering
– Silicon lattice structure
– p-type and n-type semiconductors
– p-n junction diode
– n-MOS and p-MOS transistors
– Transistors as switches
– CMOS NOT, NAND, NOR gates

0: Introduction CMOS VLSI Design 4th Ed. 3

 Silicon Lattice
 Transistors are built on a silicon substrate
 Silicon is a Group IV material (1s2 2s22p6 3s23p2)
 Forms crystal lattice with bonds to four neighbors

Si Si Si

Si Si Si

Si Si Si

0: Introduction CMOS VLSI Design 4th Ed. 4

 Dopants (Impurity)
 Silicon is a semiconductor
 Pure silicon has no free carriers and conducts poorly
 Adding dopants increases the conductivity
 Group V: extra electron (n-type)
 Group III: missing electron, called hole (p-type)

Si Si Si Si Si Si
- +

+ -
Si As Si Si B Si

Si Si Si Si Si Si

0: Introduction CMOS VLSI Design 4th Ed. 5

 p-n Junctions
 A junction between p-type and n-type semiconductor
forms a diode.
 Current flows only in one direction

p-type n-type

anode cathode

0: Introduction CMOS VLSI Design 4th Ed. 6

 Power Supply Voltage
 GND = 0 V
 In 1980’s, VDD = 5V
 VDD has decreased in modern processes
– High VDD would damage modern tiny transistors
– Lower VDD saves power
 VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …

0: Introduction CMOS VLSI Design 4th Ed. 7

 nMOS Transistor
 Four terminals: gate, source, drain, body
 Gate – oxide – body stack looks like a capacitor
– Gate and body are conductors
– SiO2 (oxide) is a very good insulator
– Called metal – oxide – semiconductor (MOS)
capacitor Source Gate Drain
Polysilicon
– Even though gate is SiO2
no longer made of metal*
n+ n+
Body
p bulk Si
* Metal gates are returning today!

0: Introduction CMOS VLSI Design 4th Ed. 8

 nMOS Operation
 Body is usually tied to ground (0 V)
 When the gate is at a low voltage:
– P-type body is at low voltage
– Source-body and drain-body diodes are OFF
– No current flows, transistor is OFF
Source Gate Drain
Polysilicon
SiO2

0
n+ n+
S D
p bulk Si

0: Introduction CMOS VLSI Design 4th Ed. 9

 nMOS Operation Cont.
 When the gate is at a high voltage:
– Positive charge on gate of MOS capacitor
– Negative charge attracted to body
– Inverts a channel under gate to n-type
– Now current can flow through n-type silicon from
source through channel to drain, transistor is ON
Source Gate Drain
Polysilicon
SiO2

1
n+ n+
S D
p bulk Si

0: Introduction CMOS VLSI Design 4th Ed. 10

 pMOS Transistor
 Similar, but doping and voltages reversed
– Body tied to high voltage (VDD)
– Gate low: transistor ON
– Gate high: transistor OFF
– Bubble indicates inverted behavior
Source Gate Drain
Polysilicon
SiO2

p+ p+

n bulk Si

0: Introduction CMOS VLSI Design 4th Ed. 11

 Transistors as Switches
 We can view MOS transistors as electrically
controlled switches
 Voltage at gate controls path from source to drain
g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s

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 CMOS Inverter

A Y VDD
0 1
1 0 OFF
ON
0
1
A Y
ON
OFF

A Y
GND
0: Introduction CMOS VLSI Design 4th Ed. 13
 CMOS NAND Gate
A B Y
0 0 1 ON
OFF
OFF
ON OFF
ON
0 1 1
1
Y
0
1 0 1
A ON
OFF
1 1 0 0
1
0
1
B OFF
ON
OFF
ON

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 CMOS NOR Gate
A B Y
0 0 1 A
0 1 0
1 0 0 B
1 1 0 Y

0: Introduction CMOS VLSI Design 4th Ed. 15

 3-input NAND Gate
 Y pulls low if ALL inputs are 1
 Y pulls high if ANY input is 0

Y
A
B
C

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 CMOS Gate Design
 Activity:
– Sketch a 4-input CMOS NOR gate

A
B
C
D
Y

1: Circuits & Layout CMOS VLSI Design 4th Ed. 17

 CMOS
 CMOS logic gates
– nMOS pull-down network pMOS

– pMOS pull-up network pull-up

network
inputs
– a.k.a. static CMOS output

nMOS
pull-down
network
Pull-up OFF Pull-up ON
Pull-down OFF Z (float) 1

Pull-down ON 0 X (crowbar)

1: Circuits & Layout CMOS VLSI Design 4th Ed. 18

 Series and Parallel
 nMOS: 1 = ON a a a a a
0 0 1 1
g1


g2
pMOS: 0 = ON b
0
b
1
b
0
b
1
b
(a) OFF OFF OFF ON

 Series: both must be ON a a a a a

 Parallel: either can be ON g1

g2
0

0
0

1
1

0
1

1
b b b b b
(b) ON OFF OFF OFF

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(c) OFF ON ON ON

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(d) ON ON ON OFF

1: Circuits & Layout CMOS VLSI Design 4th Ed. 19

Conduction Complement
 Complementary CMOS gates always produce 0 or 1
 Ex: NAND gate
– Series nMOS: Y=0 when both inputs are 1
– Thus Y=1 when either input is 0
– Requires parallel pMOS Y
A
B
 Rule of Conduction Complements
– Pull-up network is complement of pull-down
– Parallel -> series, series -> parallel
 Compound gates can do any inverting function

1: Circuits & Layout CMOS VLSI Design 4th Ed. 20

 Compound Gates
 Steps for building an arbitrary CMOS compound
gate:
– Pull down network:
• series nMOS transistors for inputs/signals that
are “AND”ed together
– Example: AB or (A+BC)D
• parallel nMOS transistors for inputs/signals that
are “OR”ed together
– Example: A+B or (ABC)+D
• The term “signal” is used to describe an intermediate
value which are generated from inputs. Here A,B,C,D are
inputs but A+BC or ABC can be called signal
0: Introduction CMOS VLSI Design 4th Ed. 21
 Compound Gates
 Steps for building an arbitrary CMOS compound
gate:
– Pull up network:
• Just follow the CONDUCTION COMPLIMENT
rule!!
• Parallel connections in pull-down network will
be redrawn in series for pull-up network,
between the same inputs/signals
• using pMOS transistors instead of nMOS

0: Introduction CMOS VLSI Design 4th Ed. 22

 Compound Gates
 Ex:
A C A C
B D B D
(a) (b)

C D
A B C D
A B
(c)
(d)

C D
A
A B
B
Y Y
C
A C
D
B D
(f)

(e)

1: Circuits & Layout CMOS VLSI Design 4th Ed. 23

 Example: O3AI
 Y   A  B  C  D

A
B
C D
Y
D
A B C

1: Circuits & Layout CMOS VLSI Design 4th Ed. 24