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Prepared By:
Pratpal Singh
Lecturer
AIMCA
Introduction
•A digital system is an interconnection
of digital h/w modules.
•Vary in size
•Modular approach of digital
components (registers, decoders,
arithmetic elements, and control logic)
•Modules connected with common data
and control paths.
Microoperations
•Digital modules are defined by the registers they contain and
the operations that are performed on the data stored in them.
•The elementary operations executed on data stored in
registers are called microoperations.
•Ex: shift, count, clear, and load.
•The internal hardware organization of computer is defined
by:
•1. The set of registers it contains and their function.
•2. The sequence of microoperations performed on the binary
information stored in the registers.
•3. The control that initiate the sequence of microoperations.
Register Transfer Language
•For a sequence of microoperations we can use
symbols.
•The symbolic notation used to describe the
microoperation transfers among registers is called
a Register Transfer Language.
Register Transfer
•Computer registers are designated by capital
letters(sometimes followed by numbers).
•Ex: PC, MAR, R1
•The individual flip flops are numbered from 0 to n-1.
R1 7 6 5 4 3 2 1
R2 PC(H) PC(L)
(c) Numbering of bits (b) Divided into two parts
R1
Block Diagram
Register Transfer
4- Line
Common
S1 Bus
S0
4x1 M3 4x1 M2 4x1 M1 4x1 M0
32 1 0 32 1 0 32 1 0 32 1 0
D2 C2 B2 A2 D1 C1 B1 A1 D0 C0 B0 A0
C2 C1 C0 B2 B1 B0 A2 A1 A0
D2 D1 D0
3 21 0 3 210 32 1 0 3 21 0
Register D Register C Register B
Register A
•Each registers has 4 bits, numbered 0 through 3.
•Bus consists four 4x1 multiplexers each having four data
inputs and two selection inpouts, S1 and S0.
•In General, S1 S0 Reg. Selected
•If we have k registers of n bits 0 0 A
0 1 B
•We needed 1 0 C
•The no. of multiplexers=n 1 1 D
•Size of MUX=k x 1
•Q.) A common bus of 8 registers of 16 bits each requires
•MUX=16
•Size=8x1
•Selection Lines=3
Three State Bus Buffer
•A three state gate is a digital circuit that have three
states.
•Three state gate has three states, i.e. 0, 1 and high
impedance state (open circuit).
Bus Line with three state buffers.
•Only one three-state gate will have access to bus-line
while all other buffers are maintained at high
impedance state.
•To ensure this we use the decoders.
•When Enable (E) is equal to 0, the bus will be in high
impedance state and all buffers are disabled.
•When Enable input is active, one of the one of the
buffer will be active, depending on Select input of
decoder.
•To construct a common bus for four registers of n bits
each using three state buffers, we need n circuits with
four buffers in each .
Arithmetic Microoperations
•The microoperations generally classified into four
categories:
•1. Register Transfer microoperations transfer binary
information from one register to another.
•Arithmetic microoperations perform arithmetic
operations on numeric data stored in registers.
•Logic microoperations perform bit manipulation
operations on non numeric data stored in registers.
•Shift microoperations perform shift operations on
data stored in registers.
Arithmetic Microoperations
Binary Adder
Binary Adder Subtractor
Arithmetic Circuit
Arithmetic Circuit
•When S1S0 = 11 and Cin =0 Then
•Output is A-1 (Decrement) because 1111 is 2`s complement
of 0001.
•So A + 2`s complement of 1 is A-1.
•Circular Shift:
•Also Known as rotate operation.
•It circulates the bits of the register around the two
ends without loss of information.
•This is accomplished by connecting the serial output
of the register to the serial input.
Arithmetic Shift
•It shifts a signed binary number to the left or right.
•An arithmetic shift left multiplies a signed binary
number by 2 and
•An arithmetic shift right divides the number by 2.
•Arithmetic shifts must leave the sign bit unchanged
because the sign of the number remains the same on
multiplication or division.
•The left most bit holds the sign bit.
•The sign bit is 0 for + and 1 for -.
•Negative numbers are in 2’s complement form.
•The arithmetic shift right leaves the sign bit
unchanged.
•And shift the number including the sign bit to the
right.
•In left shift, Rn-2 receives the bit from Rn-1 and so on.
•The arithmetic shift left inserts a 0 into R 0.
•The initial bit of Rn-1 is lost and replaced by Rn-2.
•A sign reversal occur if the bit Rn-1 changes in value
after shift.
•This happens if the multiplication by 2 causes
overflow.
•An overflow occur after after an arithmetic shift left
if initially, before the shift, Rn-1 is not equal to Rn-2.
•An overflow flip flop can be used to detect an
arithmetic overflow.
•Vs= Rn-1 EXR Rn-2
•If Vs=0, There is no overflow.
•If Vs=1, There is an overflow and sign reversal after
shift.
Hardware Implementation
Function Table For Shifter
•A combinational circuit shifter circuit can be
constructed with multiplexers.
•A four bit shifter has four data inputs, A 0 through A3.
•And four data outputs, H0 through H3.
•There are two serial inputs, one for shift left (I L) and
other for shift right (IR).
•When the selection input S=0
•The input data are shifted right (down in diagram).
•When the selection input S=1
•The input data are shifted left (up in diagram).
•A shifter with n data inputs and output, requires n
multiplexers.
Arithmetic Logic Shift Unit
Arithmetic Logic Shift Unit