Computer Architecture and Networks

Processors
(Instruction Pipeline)
Bijay Babu Regmi
stw0010@softwarica.edu.np
Computer Components
As discussed earlier, Von Neumann Architecture is based on three key concepts:

● Data and instructions are stored in a single read-write memory.

● The contents of this memory are addressable by location, without regard to the type of data contained there.

● Execution occurs in a sequential fashion (unless explicitly modified) from one instruction to the next.

An alternative to the Von Neumann Architecture is the Harvard Architecture.

Components
● The Control Unit and the Arithmetic and Logic Unit constitute the Central Processing Unit

● Data and instructions need to get into the system and results need to get out

Input/output

● Temporary storage of code and results is needed

Main memory
Computer Components: Top Level View
Contd...
● The CPU exchanges data with memory. For this purpose, it typically makes use of
two internal (to the CPU) registers: a memory address register (MAR), which
specifies the address in memory for the next read or write, and a memory buffer
register (MBR), which contains the data to be written into memory or receives the
data read from memory.
● Similarly, an I/O addresses register (I/OAR) specifies a particular I/O device.
● An I/O buffer (I/OBR) register is used for the exchange of data between an I/O
module and the CPU.
● A memory module consists of a set of locations, defined by sequentially numbered
addresses. Each location contains a binary number that can be interpreted as either an
instruction or data.
● An I/O module transfers data from external devices to CPU and memory, and vice
versa. It contains internal buffers for temporarily holding these data until they can be
Processor Organization
The processor must be able to do the following:

● Fetch instruction: The processor reads an instruction from memory (register, cache,
main memory).
● Interpret instruction: The instruction is decoded to determine what action is required.
● Fetch data: The execution of an instruction may require reading data from memory or
an I/O module.
● Process data: The execution of an instruction may require performing some
arithmetic or logical operation on data.
● Write data: The results of an execution may require writing data to memory or an I/O
module.
● In order to do these things the processor needs to store some data temporarily
and therefore needs a small internal memory (registers).
CPU with the System Bus
CPU Internal Structure
Basic Instruction Cycle
● Use the simplified two-step description which are referred to as fetch cycle and
execute cycle.
● At the beginning of each instruction cycle, the processor fetches an instruction from
memory.
● After an instruction has been interpreted, the processor performs (executes) the
required action.
Interrupt
Mechanism by which other modules (e.g. I/O) may interrupt normal sequence of processing

Classes of Interrupts:
Instruction Cycle
An instruction cycle comprises of the following stages:

● Fetch: The instruction is fetched from memory address that is stored in PC(Program
Counter) and stored in the instruction register IR. At the end of the fetch operation,
PC is incremented by 1 and it then points to the next instruction to be executed.
● Execute: Interpret the opcode and perform the indicated operation.
● Interrupt: If interrupts are enabled and an interrupt has occurred, hold on the current
operation and response to the interrupt.
Instruction Cycle with Interrupts
● It is the process by which a computer retrieves a program instruction from its memory, determines what
actions the instruction requires, and carries out those actions.
● After the execute cycle is completed, a test is made to determine if an interrupt was enabled (e.g. so that
another process can access the CPU)
● If not, instruction cycle returns to the fetch cycle.
● If so, the interrupt cycle might performs the tasks like move the current value of PC into MBR, move the PC-
save-address into MAR, etc
Flow chart of Instruction Cycle
Multiple Interrupts
When multiple interrupts do occur then the computer deals in the following ways:

Disable interrupts

● Processor will ignore further interrupts whilst processing one interrupt.

● Interrupts remain pending and are checked after first interrupt has been processed.
● Interrupts handled in sequence as they occur.

Define priorities

● Low priority interrupts can be interrupted by higher priority interrupts.

● When higher priority interrupt has been processed, processor returns to previous
interrupt.
Register Organization
Register organization is the arrangement of the registers in the processor. Register organization show how registers
are selected and how data flow between register and ALU. Depending on the roles played by the registers they can
be categorized into two types:

User Visible Register:

● These registers are visible to the assembly or machine language programmers and they use them effectively
to minimize the memory references in the instructions.
● General Purpose Register, Data Register, Address Register and Condition Codes are the types of User Visible
Register.

Control and Status Register:

● The control and status register holds the address or data that is important to control the processor’s operation.
The most important thing is that these registers are not visible to the users.
● Program Counter, Instruction Register, Memory Address Register and Memory Buffer Register are the types
of Control and Status Register.
Program Status Word (PSW)
A collection of information that encapsulates the basic execution state of a program at any instant. It permits an
interrupted process to resume operation after the interrupt has been handled. A PSW consists of the following flags:

● Sign Flag (bit 7): Contains the sign bit of the result of the last arithmetic operation. 0 for positive and 1 for
negative number.
● Zero Flag (bit 6): Set when the result is 0.
● Carry Flag (bit 0): Set if an operation resulted in a carry (addition) into or borrow (subtraction) out of a high-
order bit. Used for multiword arithmetic operations.
● Equal: Set if a logical compare result is equality.
● Overflow Flag (bit 11): Used to indicate arithmetic overflow.
● Interrupt Enable/Disable: Used to enable or disable interrupts.
● Supervisor: Indicates whether the processor is executing in supervisor or user mode.

Other Status flag include:

Parity flag (bit 2): If LSB of result is even number, set parity flag.

Adjust Flag (bit 4): Set if arithmetic operation generate carry or borrow out of 3 bits result. Commonly used in
Example:
If the last operation performed on a computer with a 8-bit word (2’s Complement
representation) was an addition in which the two operands were 00010010 and 01000011,
what would be the value of the following flags?

● Carry
● Zero
● Overflow
● Sign
● Even Parity
● Half-Carry
Solution:
00010010 + 01000011 = 01010101

Carry = 0; Zero = 0; Overflow = 0; Sign = 0; Even parity = 1; Half-carry = 0.

Now repeat the problem with the addition of 11111111 and +1.
Pipelining Strategy
● Pipelining is a technique where multiple instructions are overlapped during execution. Pipeline is divided
into stages and these stages are connected with one another to form a pipe like structure. Instructions enter
from one end and exit from another end.
● In pipeline system, each segment consists of an input register followed by a combinational circuit. The
register is used to hold data and combinational circuit performs operations on it. The output of combinational
circuit is applied to the input register of the next segment.
Pipeline Principle
The decomposition of the instruction processing by 6 stages is the following.
● Fetch Instruction (FI): Read the next expected introduction into a buffer
● Decode Instruction (DI): Determine the opcode and the operand specifiers
● Calculate Operands (CO): Calculate the effective address of each source operand.
This may involve displacement, register indirect, indirect or other forms of address
calculations.
● Fetch Operands (FO): Fetch each operand from memory. Operands in register need
not be fetched.
● Execute Instruction (EI): Perform the indicated operation and store the result, if
any, in the specified destination operand location.
● Write Operand (WO): Store result in memory.
Timing Diagram for Instruction Pipeline Operation
Pipeline Hazards
There are situations, called hazards, that prevent the next instruction in the instruction stream from executing during
its designated cycle. There are three classes of hazards:

● Structured Hazard
● Data Hazard
● Control Hazard

Structured Hazards: They arise from resource conflicts when the hardware cannot support all possible combinations
of instructions in simultaneous overlapped execution.

Data Hazards: They arise when an instruction depends on the result of a previous instruction in a way that is
exposed by the overlapping of instructions in the pipeline.

Control Hazards: They arise from the pipelining of branches and other instructions that change the PC.
Types of Data Hazards
● Read after write (RAW), or true dependency

• An instruction modifies a register or memory location

• Succeeding instruction reads data in memory or register location

• Hazard occurs if the read takes place before write operation is complete
● Write after read (WAR), or antidependency

• An instruction reads a register or memory location

• Succeeding instruction writes to the location

• Hazard occurs if the write operation completes before the read operation takes place
● Write after write (WAW), or output dependency

• Two instructions both write to the same location

• Hazard occurs if the write operations take place in the reverse order of the intended sequence
Multiple Streams
● A simple pipeline suffers a penalty for a branch instruction because it must choose one of two instructions to
fetch next and may make the wrong choice
● A brute-force approach is to replicate the initial portions of the pipeline and allow the pipeline to fetch both
instructions, making use of two streams

Drawbacks:
• With multiple pipelines there are contention delays for access to the registers and to memory
• Additional branch instructions may enter the pipeline before the original branch decision is resolved
Loop Buffer
● Small, very-high speed memory maintained by the instruction fetch stage of the pipeline and containing the n
most recently fetched instructions, in sequence
● Benefits:
Instructions fetched in sequence will be available without the usual memory access time
• If a branch occurs to a target just a few locations ahead of the address of the branch instruction, the target will
already be in the buffer
• This strategy is particularly well suited to dealing with loops
● Similar in principle to a cache dedicated to instructions
• Differences:

• The loop buffer only retains instructions in sequence

• Is much smaller in size and hence lower in cost

Superscalar Processors
● Superscalar approach is the ability to execute instructions independently and
concurrently in different pipelines.
● The concept can be further exploited by allowing instructions to be executed in an
order different from the program order.
Instruction Level Parallelism
● Instruction Level Parallelism (ILP) is a measure of how many operations in a
computer program can be performed in parallel at the same time.
● A combination of compiler based optimisation and hardware techniques can be used
to maximise instruction level parallelism.

Demerits:

● True data dependency

● Procedural dependency
● Resource conflicts
● Output dependency
● Anti dependency
References

● Computer Organization and Architecture – Designing for Performance (10th Edition),

William Stallings

● Computer Organization and Design – The Hardware/Software Interface (5th Edition),

David A. Patterson & John L. Hennessy