FLIP FLOPS

What is flip flop?

A digital computer need a device which can store information.

A flipflop is binary storage device.
It can store a binary bit either 0 or 1.
It is also called a latch or multi vibartor

Two important characteristics.

1. Flip flop is a BI stable device it can store single bit either 0 or 1.

2. Flip flop has two outputs - they are complement to each other.
Types of flip flops

1. SR FF
2. D FF
3. JK FF
4. T FF
SR LATCH

S Q
SR LATCH
R Q’
 SR-Latch (SET-RESET Latch)

R Q
2

1 Q’
S
SR-Latch ( Using NAND gate)
Characteristic table or Truth Table
INPUTS OUTPUTS

S R Qt+1 Qt+1
NO CHANGE
0 0 Qt Qt
0 1 0 1 SET

1 0 1 0 RESET

1 1 - - INDETERMINATE
 What is a Clock?

HIGH

LOW

We can define a clock signal as a particular type of signal that oscillates between a high and a low
state.
 What is a Clock?

Negative/ Falling edge

HIGH

LOW
t

Positive /Rising Edge

Flip Flop
Flip-flops are synchronous bistable devices, also known as bistable
multivibrators.
In this case, the term synchronous means that the output changes state only at
a specified point (leading or trailing edge) on the triggering input called the
clock (CLK)
That is, changes in the output occur in synchronization with the clock.
SR FF

S Q
C SR FF
R Q’
 SR FF- LOGIC CIRCUIT
R
R Q
2
CLK

1 Q’
S S
SR FF- TRUTH TABLE
S R C Qt+1 Qt+1 Operation
0 0 Rising edge ( ) Qt Qt No Change

0 1 Rising edge ( ) 0 1 Reset

1 0 Rising edge ( ) 1 0 Set

1 1 Rising edge ( ) ? ? Unstable

 D Flip Flop

The D flip flop is a flip flop with a single data input D and a clock input C.
Therefore it is called Data flip flop.
The D flip flop is also known as delay flip flop.
The data at D input is delayed by one clock pulse before it gets to the output Q.
Logic Symbol Truth Table

 D C Q State

0 Rising 0 1 Reset (stores

edge 0)

1 Rising 1 0 Set (stores (1)

edge
RS FLIP Flop as D Flip Flop
Commercial D Flip flop
J-K Flip-Flop
J K C Q Operation
0 0 Rising Hold (no change)
edge
0 1 Rising 0 1 Reset
edge
1 0 Rising 1 0 Set
edge
1 1 Rising Toggle
edge
Racing

Toggling more than once during one clock cycle in JK flip flop.
 
The racing condition in JK flip flops can be avoided by using,
 
A negative edge triggered type of JK flip flop
Master slave JK flip flop can be used
 INPUTS OUTPUTS

PRESET CLEAR CLOCK J K Q Q’

0 1 X X X 1 0

1 0 X X X 0 1
1 1 0 0 Q Q’
1 1 0 1 0 1
1 1 1 0 1 0
1 1 1 1 Q’ Q
T- Flip Flop
The Master-Slave JK Flip-flop