Cadence 实验系列 13_

RTL 编译和束缚 _RTL compiler & Encounter conformal

2010.12.23
 RTL compiler(RC)
 Introduction

 Role in IC design

 GUI interface

 Synthesis flow
 Introduction
 RC is a fast,high capacity synthesis
solution for demanding chip designs

 ‘Global focused synthesis’ results in

rapid timing closure
 Introduction
 综合是前端设计的重要步骤

 HDL 代码翻译成门级网表 netlist

 约束条件（达到面积，时序等参数标准）

 需特定工艺库

 评价标准：面积，速度，功耗
 Synthesis tool
 IC 设计综合工具包括 Synopsis DC 和
Cadence RC ；
 在 FPGA 端，常用的综合工具有
Synplicity synplify 和 Xilinx XST
 Synthesis
 综合的过程分为两步，首先将 HDL 描述语
言翻译成与工艺库无关的门级网表文件，
然后通过综合工具优化，映射到跟具体工
艺库相关的门级网表。
 RTL compiler(RC)
 Introduction

 Role in IC design

 GUI interface

 Synthesis flow
 Role in IC design
 前端设计
IC process
 Advantage
 时序收敛的全局综合工具

 提高芯片性能

 缩短设计时间

 提供高质量的硅片（ Qos ）
 RTL compiler(RC)
 Introduction

 Role in IC design

 GUI interface

 Synthesis flow
 Start GUI
 命令符： rc -gui
 General View
Manu bar

HDL Schematic Physical

Logical
viewer viewer viewer
viewer
Manu bar
Manu bar
Logical viewer and HDL vewer
Schematic viewer
 RTL compiler(RC)
 Introduction

 Role in IC design

 GUI interface

 Synthesis flow
Synthesis flow
Synthesis flow
 set_attribute lib_search_path
<full_path_of_technology_library_directory> /
 set_attribute hdl_search_path <full_path_of_hdl_files_directory>
 set_attribute library <technology_library> /
 read_hdl <hdl_file_names>
 elaborate <top_level_design_name>
 set clock [define_clock –period <periodicity> –name
<clock_name> [clock_ports]]
 external_delay –input <specify_input_external_delay_on_clock>
 external_delay –output
<specify_output_external_delay_on_clock>
 synthesize -to_mapped
 report timing > <specify_timing_report_file_name>
 report area > <specify_area_report_file_name>
 write –mapped > <specify_netlist_name>
 write_script > <script_file_name>
Step1 Invoke the RC
rc －
gui
 Step2 Specify the library
 设置工艺库存放路径
set_attribute lib_search_path
/export/home1/STSY_BB/BB_y29/lib/S
ynopsys

 指定要加载的工艺库
set_attribute library {hjtc18_tt.lib}
 Step3 Load HDL files
Load Mips sources
 read_hdl
/export/home1/STSY_BB/BB_y29/mips_source/MCore.v
 read_hdl
/export/home1/STSY_BB/BB_y29/mips_source/alu_v2.v
 read_hdl /export/home1/STSY_BB/BB_y29/mips_source/biu.v
 read_hdl
/export/home1/STSY_BB/BB_y29/mips_source/branch.v
 read_hdl
/export/home1/STSY_BB/BB_y29/mips_source/core.v
 read_hdl …….
tcl script
 Step4 Perform Elaboration
 Builds data structures
 Infers registers in the design
 Performs higher-level HDL
optimization, such as dead code
removal
 Checks semantics
 Step4 Perform Elaboration
 Elaborate
建立一个结构级描述，该描述与工艺无关

Schematic
viewer
 Step5 Apply Constraints
Constraint Commands
 define_clock
定义时钟输入波形
 external_delay

设定输入输出相对时钟的延时
 path_delay

设置路径时序约束
 其他：
create_mode,define_cost_groud,multi_cycl
e
 Step6 Synthesize
 set MAP_EFF high
 synthesize -to_mapped eff$MAP_EFF
-no_incr
 Step7 Save design
保存综合的网表文件
write -mapped > MCore_synth.v

保存约束文件（ sdc ）
write_sdc > MCore_tst.sdc
 Step8 Analyze
 输出功耗报表文件
report power > MCore.power.rpt

 输出时序报表文件
report timing > MCore.timing.rpt
Step8 Analyze timing and power
 tcl script-- 命令行批量处理
 set_attribute lib_search_path /export/home1/STSY_BB/BB_y29/lib/Synopsys
 ## This defines the libraries to use
 set_attribute library {hjtc18_tt.lib}
 read_hdl /export/home1/STSY_BB/BB_y29/mips_source/MCore.v
 read_hdl /export/home1/STSY_BB/BB_y29/mips_source/alu_v2.v
 read_hdl /export/home1/STSY_BB/BB_y29/mips_source/biu.v
 read_hdl /export/home1/STSY_BB/BB_y29/mips_source/branch.v
 read_hdl /export/home1/STSY_BB/BB_y29/mips_source/core.v
 read_hdl /export/home1/STSY_BB/BB_y29/mips_source/cp0.v
 read_hdl /export/home1/STSY_BB/BB_y29/mips_source/decode.v
 read_hdl /export/home1/STSY_BB/BB_y29/mips_source/exec.v
 read_hdl /export/home1/STSY_BB/BB_y29/mips_source/fifo.v
 read_hdl /export/home1/STSY_BB/BB_y29/mips_source/idtlb.v
 read_hdl /export/home1/STSY_BB/BB_y29/mips_source/irq.v
 read_hdl /export/home1/STSY_BB/BB_y29/mips_source/jtlb.v
 read_hdl /export/home1/STSY_BB/BB_y29/mips_source/mcore_define.v
 read_hdl /export/home1/STSY_BB/BB_y29/mips_source/mdu_v2.v
 read_hdl /export/home1/STSY_BB/BB_y29/mips_source/mem_stage.v
 read_hdl /export/home1/STSY_BB/BB_y29/mips_source/mmu.v
 read_hdl /export/home1/STSY_BB/BB_y29/mips_source/pag.v
 read_hdl /export/home1/STSY_BB/BB_y29/mips_source/pipeline.v
 read_hdl /export/home1/STSY_BB/BB_y29/mips_source/reg_ctrl.v
 read_hdl /export/home1/STSY_BB/BB_y29/mips_source/regfile.v
 read_hdl /export/home1/STSY_BB/BB_y29/mips_source/shifter.v
 read_hdl /export/home1/STSY_BB/BB_y29/mips_source/tlb.v
 read_hdl /export/home1/STSY_BB/BB_y29/mips_source/tlb_page.v
 read_hdl /export/home1/STSY_BB/BB_y29/mips_source/trap.v
 read_hdl /export/home1/STSY_BB/BB_y29/mips_source/write_back.v
 tcl script
 ## This buils the general blocek
 elaborate
 ##this allows you to define a clock and the maximum allowable delays
 ## READ MORE ABOUT THIS SO THAT YOU CAN PROPERLY CREATE A TIMING FILE
 define_clock -name clk -period 5000 [find / -port clk]
 external_delay -input 100 -clock [find / -clock clk] -edge_fall [all_inputs]
 external_delay -output 100 -clock [find / -clock clk] -edge_fall [all_outputs]
 set_attribute wireload_mode enclosed
 set_attribute max_dynamic_power 0.0 MCore
 set_attribute max_leakage_power 0.0 MCore
 ##This synthesizes your code
 set MAP_EFF high
 synthesize -to_mapped -eff $MAP_EFF -no_incr
 ## This writes all your files
 ## change the tst to the name of your top level verilog
 ## CHANGE THIS LINE: CHANGE THE "accu" PART REMEMBER THIS
 ## FILENAME YOU WILL NEED IT WHEN SETTING UP THE PLACE & ROUTE
 write -mapped > MCore_synth.v
 ## THESE FILES ARE NOT REQUIRED, THE SDC FILE IS A TIMING FILE
 ##write_script > script
 write_sdc > MCore_tst.sdc
 ##report and annlyze power and timing
 report power > MCore.power.rpt
 report timing > MCore.timing.rpt
 Encounter conformal
 Introduction

 EC’ necessary

 Process flow
 Introduction
 EC 是等效功能验证工具，即验证寄存器级
电路和映射后的门级电路是否等效
 对庞大而复杂的设计，仿真速度不再是主
要的验证流程评估基准
 高级验证流程以互补的方式确保边际错误
情况被及时发现
 Introduction
 头号设计瓶颈 - 验证
 设计的整体复杂性不断增强，设计验证任务
也随之变得复杂，硬件验证本身越来越具有
挑战性，验证时间正在变得越来越长
 调查表明，只有 39% 的设计在第一次硅验
证时没有缺陷， 60% 包含逻辑或功能缺陷
， 20% 以上需要三次或者多次硅验证。另
外一项 Collett 调查还表明，全部工程时间
的约 50% 是验证时间。
 Encounter conformal
 Introduction

 EC’ necessary

 Process flow
 EC’ necessary

 综合出的门级网表与 RTL 设计在逻辑和

时序上应完全一致。但是某些书写风格和
设计思路却会造成两者不一致的情况。
 看下面的例子 （不完整敏感表）
 One example
 module OR_GATE_A (OUT_A, IN1, IN2);
 output OUT_A;
 input IN1, IN2;
 reg OUT_A;
 always @(IN1 or IN2)
 OUT_A = IN1 | IN2;
 endmodule
 /////////////////////////////////////////////////////////////////////////////
 再看下面的例子，敏感量列表只包含 IN1 。
 /////////////////////////////////////////////////////////////////////////////
 module OR_GATE_B (OUT_B, IN1, IN2);
 output OUT_B;
 input IN1, IN2;
 reg OUT_B;
 always @(IN1)
 OUT_B = IN1 | IN2;
 endmodule
 EC’ necessary
 为保证 RTL 设计与综合后网表一致，注意
：
 1 ）结合所选逻辑综合工具的特点，使用合
适的书写方式
 2 ）了解所使用的标准库单元的速度
 3 ）明确硬件电路时钟的频率，并估计复杂
运算在一个周期内能否完成
 Encounter conformal
 Introduction

 EC’ necessary

 Process flow
Process flow
 Step1 Start conformal

 lec
Step2 Read RTL
Step3 Read Gate Netlist
 Step4 Run Comparison

RTL 文件 Gate Netlist

Thank you
！