CPU Organization

Bindu Agarwalla
 CPU Organization
1.Single Accumulator Organization (One Address Instruction)

2. General Register Organization (Two and Three Address Instruction)

3.Stack Organization (Zero Address Instruction)

To understand the topic we will take an example and will discuss all the
organizations.

X=(A+B) * (C+D)
 CPU Organization
1.Three Address Instruction:X=(A+B) * (C+D)

General format:
Opcode destination, src1, src2
Note: The order of operands vary from architecture to architecture.

ADD R1, A, B //R1←Mem[A] +Mem[B]

ADD R2, C, D //R2←Mem[C] +Mem[D]

MUL X, R1, R2 //Mem[X]←[R1] * [R2]

 CPU Organization
1.Two Address Instruction: X=(A+B) * (C+D)

General format:
Opcode src1/dest, src2
Note: The order of operands vary from architecture to architecture.

MOV R1, A //R1←Mem[A]

ADD R1, B //R1←[R1] +Mem[B]

MOV R2, C //R2←Mem[C]

ADD R2, D //R2←[R2] +Mem[D]

MUL R1, R2 //R1←[R1] * [R2]

MOV X,R1 //Mem[X]←[R1]

 CPU Organization
1.One Address Instruction: X=(A+B) * (C+D)

This uses accumulator(AC) register for all data manipulations. Here AC

is assumed to be one of the operands for all the instructions.
LOAD: from memory to accumulator
STORE: From accumulator to memory

LOAD A //Acc←Mem[A]

ADD B //Acc←[Acc] +Mem[B]

STORE T //Mem[T] ← [Acc]

LOAD C //Acc←[Mem[C]

ADD D //Acc←[Acc] +Mem[D]

MUL T //Acc←[Acc] *Mem[T]

STORE X //Mem[X]←[Acc]
 CPU Organization
1.Zero Address Instruction: X=(A+B) * (C+D)

A stack-organized computer doesn't use the address field for the

instructions like ADD, MUL, XOR etc. Operand is specified only for
Push and Pop operations.The top two contents from the stack is popped
out and the operation is performed and then the result is pushed back
onto the stack.
PUSH A //Stack[top]←Mem[A]
PUSH B //Stack[top]←Mem[B]
ADD //Stack[top-1]←Stack[top-1]+Stack[top]
PUSH C //Stack[top]← [Mem[C]

PUSH D //Stack[top]← Mem[D]

ADD//Stack[top-1]←Stack[top-1]+Stack[top]
MUL //Stack[top-1]←Stack[top-1]*Stack[top]
POP X //X←Stack[top]
 CPU Organization
Example 2:
X:=(P+Q) * R / S + (T-U) / V
 CPU Organization
1.THREE Address Instruction: X:=(P+Q) * R / S + (T-U) / V

ADD R1, P, Q
MUL R1, R1, R
DIV R1, R1, S
SUB R2, T, U

DIV R2, R2, V

ADD X, R1, R2
 CPU Organization
1.TWO Address Instruction: X:=(P+Q) * R / S + (T-U) / V

MOV R1, P
ADD R1, Q
MUL R1, R
DIV R1, S

MOV R2, T

SUB R2, U
DIV R2, V
ADD R1, R2

MOV X, R1
 CPU Organization
1.One Address Instruction: X:=(P+Q) * R / S + (T-U) / V

LOAD P
ADD Q
MUL R
DIV S

STORE TEMP

LOAD T
SUB U
DIV V

ADD TEMP
STORE X
 CPU Organization
1.ZERO Address Instruction: X:=(P+Q) * R / S + (T-U) / V

PUSH P
PUSH Q
ADD
PUSH R

MUL

PUSH S
DIV
PUSH T

PUSH U
SUB ADD
PUSH V POP X
DIV
 CPU Organization
1RISC Instruction: X:=(P+Q) * R / S + (T-U) / V

LOAD R1, P

LOAD R2, Q
ADD R1, R1, R2
LOAD R2, R

MUL R1, R1, R2

LOAD R2, S
DIV R1, R1, R2
LOAD R2, T

LOAD R3, U
SUB R2, R2, R3 ADD R1, R1, R2
LOAD R3, V STORE X, R1
DIV R2, R2, R3
 Organization Vs Architecture
Computer Architecture is the design of the system, visible to the
assembly language programmer

What is the instruction set

How many registers
Memory addressing scheme/ addressing modes

Organization is how the architecture is implemented

How much cache memory

Implementation technology

All computers in the Intel Pentium series have the same architecture
but each version of Pentium has a different organization or
implementation
 Von Neuman's Stored Program Concept
John Von Neumann has invented a m/c in Institute of Advanced Studies
in 1945 to 1952 which is named as stored program digital computer.

It keeps its programmmed instructions as well as data in the same RAM.

Parallelism( Piplining) is not supported by this architecture.

Harvard Architecture.
 Basic Performance Equation
Program execution time (T) = (N X S)/R

Where, T is the execution Time

N is the no of instructions in execution

S is the average no of basic steps needed to execute one machine instruction.

R is the clock rate R=1/f

 Problem
Discuss the factors that affect the performance of the computer. If
a 8GHz computer takes 7 clock cycles for ALU instructions, 11
clock cycles for branch instructions and 6 clock cycles for data
transfer instructions. Then Find the total time taken by the
computer to execute the program that consists of 10 ALU
instructions, 5 branch instructions and 5 data transfer
instructions.
 Problem
Also explain how an instruction SUB R0, LocA; (meaning [R0] -
[LocA]=[LocA] ) is executed by the processor with neat diagram.
 Problem
e)A computer uses a memory unit with 256K words of 32 bits
each. A binary instruction code is stored in one word of memory.
The instruction has four parts: an indirect bit, an operation code, a
register code part to specify one of 64 registers, and an address
part. How many bits are there in the operation code, the register
code part, and the address part?

Mode Op-code Register Address

256 K = 28 × 210 = 218

Address = 18 bits

Mode = 1 bits
Register = 6 bits

Total=25 bits
op code =32-25=7 bits
 Problem
a)A computer has 64-bit instructions and 12 bit addresses. If
there are 352 three-address instructions, and 2256 no of two-
address instructions then how many one-address instructions can
be formulated?

Maximum Possible 3 address instructions are:228.

Maximum possible 2 address instructions are: (228 – 352) X 212

So, Maximum possible 1 address instructions are: ((228 – 352) X

212-2256) X 212
 Problem
b)PC does the same function as MAR, and then justify your
answer by keeping two registers instead of one.
PC always holds the address of the instruction which is being
currently executed. During the fetch phase of the instruction, the
content of PC is incremented, which points to the next instruction
of the program. If there is only PC in the processor, then during
the execution phase of the instruction, for fetching the operand the
same PC can be used and the content of PC which holds the
address of next instruction, is lost. Similarly if only MAR is
available in the processor, then same problem occurs. Hence at
any cost, two registers must be in the processor to help the
execution of the program.
 Basic Operational Concept
How an instruction is being executed?
Write a program to evaluate an expression
X=((A+B)*C)/(D-E*F+G*H) using
3-Address and also write another program to evaluate the
same expression using 0-Addess instructions only. In the
expression X,A,B,C,D,E,F,G and H are memory addresses
Thank You