Exceptions

Exception Types
• The Cortex™-M3 provides a feature-packed exception
architecture that supports a number of system
exceptions and external interrupts.
• Exceptions are numbered 1–15 for system exceptions
and 16 and above for external interrupt inputs.
• The value of the current running exception is indicated
by the special register Interrupt Program Status register
(IPSR), or from the Nested Vectored Interrupt
Controllers (NVICs) Interrupt Control State register.
List of System Exceptions
 List of External Interrupts

When an enabled exception occurs but cannot be carried out

immediately (for instance, if a higher-priority interrupt service
routine is running or if the interrupt mask register is set), it will
be pended (except for some fault exceptions1).
This means that a register (pending status) will hold the
exception request until the exception can be carried out.
 Definitions of Priority
• The Cortex-M3 supports three fixed highest-
priority levels and up to 256 levels of
programmable priority (a maximum of 128
levels of preemption).
• For example, if only 3 bits of priority level are
implemented in the design, a priority-level
configuration register will look like in the
figure shown.
 A Priority Level Register with 3 Bits
Implemented.

 A Priority Level Register with 4 Bits

Implemented
Available Priority Levels with 3-Bit or 4-Bit
Priority Width
• Using a configuration register in the NVIC
called Priority Group (a part of the Application
Interrupt and Reset Control register in the
NVIC) the priority-level configuration registers
for each exception with programmable
priority levels is divided into two halves. The
• upper half (left bits) is the preempt priority
• lower half (right bits) is the sub priority.
• The preempt priority level defines whether an
interrupt can take place when the processor is
already running another interrupt handler.

• The subpriority level value is used only when

two exceptions with the same preempt
priority level occurred at the same time. In
this case, the exception with higher
subpriority (lower value) will be handled first.
• When deciding the effective preempt priority
level and subpriority level, you must take the
following factors into account:
• Implemented priority-level configuration
registers
• Priority group setting
Example: Definition of Priority Fields in a 3-Bit
Priority Level Register with Priority Group Set
to 5.
 Vector Tables
• When an exception takes place and is being handled by the
Cortex-M3, the processor will need to locate the starting address
of the exception handler. This information is stored in the vector
table in the memory.
• By default, the vector table starts at memory address 0, and the
vector address is arranged according to the exception number
times four.
• vector table can be relocated to other memory locations in the
code or Random Access Memory (RAM) region where the RAM
is so that we can change the handlers during run time. This is
done by setting a register in the NVIC called the vector table
offset register .
Exception Vector Table After Power Up

In applications where you want to allow dynamic changing of

exception handlers, in the beginning
of the boot image, you need to have the following (at a
minimum):
• Initial main stack pointer value
• Reset vector
• NMI vector
• Hard fault vector
Interrupt Inputs and Pending Behavior
• When an interrupt input is asserted, it will be pended, which
means it is put into a state of waiting for the processor to
process the request.
• Even if the interrupt source desserts the interrupt, the
pended interrupt status will still cause the interrupt handler
to be executed when the priority is allowed.
• Once the interrupt handler is started, the pending status is
cleared automatically.
• The pending status of the interrupt can be
accessed in the NVIC and is writable, so you
can clear a pending interrupt or use software
to pend a new interrupt by setting the
pending register.
• When the processor starts to execute an interrupt, the
interrupt becomes active and the pending bit will be
cleared automatically .
• When an interrupt is active, you cannot start
processing the same interrupt again, until the interrupt
service routine is terminated with an interrupt return .
• Then the active status is cleared, and the interrupt can
be processed again if the pending status is 1. It is
possible to repend an interrupt before the end of the
interrupt service routine.
 Interrupt Active Status Set as Processor Enters Handler

Continuous Interrupt Request Pends Again After Interrupt Exit.

• If an interrupt is pulsed several times before the processor
starts processing it, it will be treated as one single interrupt
request

•If an interrupt is deserted and then pulsed again during the interrupt
service routine, it will be pended again