Introduction to RISC processor

Introduction to RISC processor

RISC
• Reduced Instruction Set Computer

• Key features
• Large number of general purpose registers
• or use of compiler technology to optimize register use
• Limited and simple instruction set
• Emphasis on optimising the instruction pipeline
 CISC and RISC
Comparison of processors
Why RISC?
 CISC and RISC
RISC Pipelining
• Most instructions are register to register
• Two phases of execution
• I: Instruction fetch
• E: Execute
• ALU operation with register input and output
• For load and store
• I: Instruction fetch
• E: Execute
• Calculate memory address
• D: Memory
• Register to memory or memory to register operation
 CISC and RISC
Introduction
֍ Based on the architecture i.e. Instruction Set of the microprocessor. 

Classification of Microprocessor

CISC RISC
Complex Instruction Set Computer Reduced Instruction Set Computer

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 Difference between CISC and RISC
CISC RISC
large number of instructions. Very fewer instructions

Some instructions with long execution times No instruction with a long execution time 

Multiple formats are supported for specifying operands Simple addressing formats are supported

CISC supports array. RISC does not supports array.

Arithmetic and logical operations can be applied to both Arithmetic and logical operations only use register 
memory and register

Implementation programs are hidden from machine level Implementation programs exposed to machine
programs level programs

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CISC and RISC
 ARM

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 ARM

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 ARM

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 ARM

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 ARM

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 ARM

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 ARM

Large registers set R0 – R15. Each is of 32 bit wide.

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 ARM Family

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 ARM

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 ARM

ARM is a load-store architecture:

Values must be loaded into registers in order to operate upon
them.
No instructions directly operate on values in memory.

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 ARM Registers
(1) ARM has sixteen registers. All are 32 bits wide.

All of the registers are general purpose.

R13 / SP which holds the stack pointer.
R14 / LR the link register which holds the callers'
return address.
R15 / PC which holds the program counter.

(2) CPSR is the current program status register. This holds

flags: results of arithmetic and logical operations.

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 ARM
Barrel Shifter
It is a functional unit testing that is used to perform the Shift and
Rotate Operations.
It provides five types of shifts and rotates
LSL – Logical Shift Left
LSR – Logical Shift Right
SR – Arithmetic Shift Right
ROR – Rotate Right
RRX – Rotate Right Extended

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 ARM

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 ARM

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 ARM

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 ARM

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 ARM

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