1.weak consistency 2.release consistency 3.entry consistency What is consistency model ? A contract between the software and memory Contract says:- if the s/w agrees to obey certain rules , then memory promises to work properly. If s/w violates the rules then correctness of memory operation is no longer guaranteed . WEAK CONSISTENCY Even if no process is allowed to touch the variable until the first process leaves the critical section. The memory can’t know whether or not a
process is in a critical section.
So has to propagate all writes to all memories in usual way. synchronization variable Better solution for synchronization process.
operations on it are used to synchronize
memory. After synchronization completes all writes done on that machine are propagated outwards And all writes done on other machines are brought in.. Weak consistency model:- three imp properties. Access to synchronization variables are sequentially consistent. No access to synchronization variable is allowed to be performed until all previous writes have completed everywhere. No data access(read or write) is allowed to be performed until all previous accesses to synchronization variables have been performed. Release consistency model. Problem in weak consistency :- the memory does not know if the access to synchronization variable is being done because the process is finished writing the shared variables or about to start reading them. If the memory could tell the difference between entering a critical region and leaving one , a more efficient implementation might be possible. To provide this information, two kinds of
synchronization variables or operations are needed
instead of one. Release consistency provides these two kinds.
1.Acquire 2.release Acquire accesses are used to tell the memory system that a critical region is about to be entered.
Release accesses say that a critical region
has just been exited. Barriers can b used instead of critical regions with release consistency. Barrier – synchronization mechanism – prevents any process from starting phase n+1 of a program until all processes have finished phase n. When process arrives at a barrier it must wait until all other processes get there 2. When last one arrives, all shared variables are synchronized and then all processes are resumed. DEPARTURE is ACQUIRE and ARRIVAL is RELEASE. Release consistency model:- three imp properties. Before an ordinary access to a shared variable is performed , all previous acquires done by the process must have completed successfully. Before a release is allowed to be performed , all previous reads and writes done by the process must have completed. The acquire and release accesses must be processor consistent. (sequential consistency is not required.) Entry consistency It requires the programmer to use acquire and release at the start and end of each critical section resp. Each ordinary shared variable is associated with synchronization variables such as lock or barrier. entry consistency model:- imp properties. An acquire access a of a synchronization variable is not allowed to perform with respect to a process until all updates to the guarded shared data have been performed with respect to that process Before an exclusive mode access to a synchronization variable by a process is allowed to perform with respect to that process , no other process may hold the synchronization variable , not even in nonexclusive mode. Ty ….