FPGA Based System Design

ENGR. RASHID FARID CHISHTI

LECTURER, DEE, FET, IIUI
CHISHTI@IIU.EDU.PK

WEEK 13

TASK AND FUNCTIONS

www.iiu.edu.pk Saturday, November 27, 2021

 Task
 In verilog task can be used to code functionality that is repeated multiple times in a module.
 A task has input, output and inout and can have its local variables.
 All the variables defined in the module are also accessible in the task.
 The task must be defined in the same module using task and endtask keywords.
 To use a task in other modules, the task should be written in a separate file and the file then should be included using an `include directive in these
modules.
 The tasks are called from initial or always blocks or from other tasks in a module.
 The task can contain any behavioral statements including timing control statements. Like module instantiation, the order of input, output and inout
declarations in a task determines the order in which they must be mentioned for calling.
 As tasks are called in a procedural block, the output must be of type reg , whereas the inputs may be of type reg or wire.
 Verilog 2001 adds a keyword automatic to the task to define a reentrant task.

 The following example designs a task FA and calls it in a loop four times to generate a 4 bit ripple
carry adder:

1. A function can enable another function but not another task.

2. Functions always execute in 0 simulation time.
3. Functions must not contain any delay, event, or timing control statements.
4. Functions must have at least one input argument. They can have more than one input.
5. Functions always return a single value. They cannot have output or inout arguments.
Tasks
1. A task can enable other tasks and functions.
2. Tasks may execute in non-zero simulation time.
3. Tasks may contain delay, event, or timing control statements.
4. Tasks may have zero or more arguments of type input, output, or inout.
5. Tasks do not return with a value, but can pass multiple values through output and inout arguments.
www.iiu.edu.pk 2 Saturday, November 27, 2021
 Task
// The following example designs a task FA and calls it in a loop four times to
// generate a 4 bit ripple carry adder:
module RCA( input [3:0] a, b, input c_in, output reg c_out, output reg [3:0] sum);
reg carry[4:0]; integer i;
task FA( input in1, in2, carry_in, output reg out, carry_out);
assign {carry_out, out} = in1 + in2 + carry_in;
endtask

always@* begin
carry[0] = c_in;
for( i=0; i<4 ; i=i+1)
begin FA(a[i], b[i], carry[i], sum[i], carry[i+1]); end
c_out = carry[4];
end
endmodule
www.iiu.edu.pk 3 Saturday, November 27, 2021
 Functions
 Verilog function is in many respects like task as it also implements code that can
be called several times inside a module.
 A function is defined in the module using function and endfunction keywords.
 The function can compute only one output. To compute this output, the function
must have at least one input.
 The output must be assigned to an implicit variable bearing the name and range of
the function.
 The range of the output is also specified with the function declaration.
 A function in Verilog cannot use timing constructs like # or @ . A function can be
called from a procedural block or continuous assignment statement.
 It may also be called from other functions and tasks, whereas a function cannot
call a task. A reentrant function can be designed by adding the automatic
keyword.
 A simple example here writes a function to implement a 2:1 multiplexer and then
uses it three times to design a 4:1 multiplexer:

www.iiu.edu.pk 4 Saturday, November 27, 2021

 Functions
module MUX4to1( input [3:0] in, input [1:0] sel, output out);
wire out1, out2;
function MUX2to1;
input in1, in2; input select;
assign MUX2to1 select ? in2:in1;
endfunction
assign out1 = MUX2to1(in[0], in[1], sel[0]);
assign out2 = MUX2to1(in[2], in[3], sel[0]);
assign out = MUX2to1 (out1 ,out2, sel[1]);
endmodule
/* stimulus for testing the module MUX4to1 */
module testFunction;
reg [3:0] IN; reg [1:0] SEL; wire OUT;
MUX4to1 mux(IN, SEL, OUT);
initial begin
www.iiu.edu.pk 5 Saturday, November 27, 2021
 Functions
IN = 1; SEL = 0;
#5 IN = 7; SEL = 0;
#5 IN = 2; SEL = 1;
#5 IN = 4; SEL = 2;
#5 IN = 8; SEL = 3;
end
initial
$monitor ( $time, " %b %b %b\n ", IN, SEL, OUT);
endmodule

www.iiu.edu.pk 6 Saturday, November 27, 2021

 Task and Function
Task
 A task can enable other tasks and functions.
 Tasks may execute in non-zero simulation time.
 Tasks may contain delay, event, or timing control statements.
 Tasks may have zero or more arguments of type input, output, or inout.
 Tasks do not return with a value, but can pass multiple values through output and
inout arguments.

Function
 A function can enable another function but not another task.
 Functions always execute in 0 simulation time.
 Functions must not contain any delay, event, or timing control statements.
 Functions must have at least one input argument. They can have more than one
input.
 Functions always return a single value. They cannot have output or inout
arguments.
www.iiu.edu.pk 7 Saturday, November 27, 2021
 Task and Function
Task
 Tasks are used for common Verilog code that contains delays, timing, event constructs, or multiple output arguments.
 Tasks can have input, output, and inout arguments
Function
 Functions are used when common Verilog code is purely combinational, executes in zero simulation time, and provides exactly one output. Functions
are typically used for conversions and commonly used calculations.
 Functions can have input arguments. In addition, they can have local variables, registers, time variables, integers, real, or events.
Task and Function Similarities
 Both tasks and functions must be defined in a module and are local to the module.
 Tasks or functions cannot have wires.
 Tasks and functions contain behavioral statements only.
 Tasks and functions do not contain always or initial statements but are called from always blocks, initial blocks, or other tasks and functions.

 Tasks are declared with the keywords task and endtask. Tasks must be used if any one of the following conditions is true for the procedure:
 There are delay, timing, or event control constructs in the procedure.
 The procedure has zero or more than one output arguments.

 The procedure has no input arguments.

// Define a module called operation that contains the task bitwise_oper

module operation;
parameter delay = 10; reg [15:0] A, B;
reg [15:0] AB_AND, AB_OR, AB_XOR;
always @(A or B) begin // whenever A or B changes in value
// invoke the task bitwise_oper. provide 2 input arguments A, B
// Expect 3 output arguments AB_AND, AB_OR, AB_XOR
// The arguments must be specified in the same order
// as they appear in the task declaration.
bitwise_oper (AB_AND, AB_OR, AB_XOR, A, B);
end
www.iiu.edu.pk 8 Saturday, November 27, 2021