Sequential Circuits

Lecture 19
 Sequential Circuit

• A sequential circuit is formed by interconnecting a

combinational circuit and storage elements.
• The storage elements are circuits that are capable of storing
binary information.
• Binary information stored in these elements at any given time
defines the state of a sequential circuit.
 Sequential Circuit

• Outputs in a sequential circuit are a function not only of the

inputs, but also of the present state of the storage elements.

• In general, we wish to store information for an indefinite time.

Sequential Circuit Example
 Types of Sequential Circuits

• Synchronous sequential circuit can be defined from the

knowledge of its signals at discrete instants of time.
• Asynchronous sequential circuit depends upon the inputs at
any instant of time and the order in continuous time in which
the inputs change.
 Implementation of Storage

• The storage can be constructed from logic

with delay connected in a closed loop.
• Figure (a) shows a buffer with gate delay tG which holds
information for time tG.
• Figure (a) and (b) hold the bit for
indefinite interval of time as the output is
again fed as input.
 Implementation of Storage

• Delay gates are usually constructed by using double inverters

• The data remains the same after
two inversions.
• Asynchronous storage circuits called latches are made in this
manner.
• Synchronization is achieved by a timing device called a clock
generator .
 Synchronous Clocked Sequential Circuit
• Synchronous sequential circuits that use clock pulses as inputs
for storage elements are called clocked sequential circuits .
• The storage elements used in the simplest form of clocked
sequential circuits are called flip-flops.
• A flip-flop is a binary storage device capable of storing one bit
of information and having timing characteristics.
 LATCHES
• A storage element can maintain a binary state indefinitely as
long as power is delivered to the circuit.
• or, until directed by an input signal to switch states
• The most basic storage elements are latches, from which flip-
flops are usually constructed
 SR Latch
• The SR latch is a circuit constructed from two cross-coupled
NOR gates.
• The latch has two inputs, labeled S for set and R for reset, and
two useful states.
 SR Latch
• Asynchronous in nature: No Clock.
• When output Q = 1 and Q’ = 0, the latch is said to be in the set
state.
• When Q = 0 and Q’ = 1, it is in the reset state.
• Under normal conditions, both inputs of the latch remain at 0 unless
the state is to be changed.
• When both inputs are equal to 1 at the same time, an undefined
state with both outputs equal to 0 occurs.
 S’R’ Latch
• The S’R’ latch is a circuit constructed from two cross-coupled
NAND gates.
• It operates with both inputs normally at 1, unless the state of
the latch has to be changed.
 S’R’ Latch
• 0 to the S’ input causes output Q to go to 1, set state.
• When the S’ input goes back to 1, it remains in the set state.
• Under normal conditions, both inputs of the latch remain at 0 unless
the state is to be changed.
• The condition that is undefined for this NAND latch is when both
inputs are equal to 0 at the same time, an input combination that
should be avoided.
 SR Latch with Control Input
• Latches can be modified by providing an additional control input.
• The control input C acts as an enable signal (clock).
• When C returns to 0, the circuit remains in its current state.
 SR Latch with Control Input
• Control input C = 0 disables the circuit so that the state of the
output does not change, regardless of the values of S and R.
• when C = 1 and both the S and R inputs are 0, the state does not
change.
• An undefined state occurs when all three inputs are equal to 1.
• SR latch with control input are used to construct other latches and
flip-flops.
 D Latch
• Eliminates the undesirable undefined state in the SR latch.
 D Latch
• D latch has only two inputs: D (data) and C (control).
• The D input is sampled when C = 1.
• If D is 1, the Q output goes to 1, set state .
• If D is 0, the Q output goes to 0, reset state.
• Also called Transparent latch.
• D latch symbol:
 Transparent Latch
• The data input of the D latch is transferred to the Q output
when the control input is enabled
Transparency Property
 Clock Cycle
• One up and one down make a clock cycle.
• Frequency is number of clock cycles per second.
• Clock up-down are also referred as high-low/enable-disable.

• D-latch saves one bit when clock pulse is low but becomes
transparent when pulse is high.
 Problem of Transparency
• D-latch works fine for half cycle (low).
• On high clock pulse it becomes transparent by showing input data as
output.
• What if some other circuit effects input (D) during high clock pulse. It
may hold wrong data when clock pulse is low.
 Problem of Transparency
• Suppose the other circuit just has an inverter.
• The output of the inverter is again connected to the input of D
latch.
• The input will oscillate (0 to 1 and 1 to 0) until the clock remains
high.
• As the result, when clock pulse is low the latch may hold
erroneous data.
Problem of Transparency
 Flip-Flop
• Solution: eliminate transparency
• Combination of two latches which separate the input and output.
• Only one latch is open at a time.
• Combination of two D-latches is called a D Flip-flop or SR flip-flop
or master-slave SR flip-flop
• Master is a D latch and the slave is an SR latch or a D latch