MOSFETs

Metal-Oxide-Semiconductor
Field Effect Transistors
 Classes of Field Effect Transistors
 Metal-Oxide-Semiconductor Field Effect
Transistor(MOSFET)
 Metal-Semiconductor Field Effect Transistor(MESFET)
 Junction Field Effect Transistor(JFET)
 High Electron Mobility Transistor or Modulation Doped
Field Effect Transistor(HEMT or MODFET)
 Fast Reverse/Fast Recovery Epitaxial Diode(FREDFET)
 DNA Field Effect Transistor
Field Effect Transistors
 The conductivity (or resistivity) of the path
between two contacts, the source and the
drain, is altered by the voltage applied to the
gate( voltage controlled resistor).
Channel Drain

Gate

Source
Types of MOSFETS
 Enhancement MOSFET
 Depletion MOSFET

◦ Enhancement mode
 A voltage must be applied to the gate to
create a conduction path between the
source and the drain.
◦ Depletion mode
 A voltage must be applied to the gate to
destroy a conduction path between the
source and the drain.
n channel Enhancement MOSFET

SiO2
p channel Enhancement MOSFET

SiO2
n channel Depletion MOSFET
p channel Depletion MOSFET

SiO2
 Symbols for n channel
Enhancement MOSFET

VGS ≥ 0V, VDS ≥ 0V

VTN is positive
Symbols for p channel Enhancement
MOSFET

VGS ≤ 0V, VDS ≤ 0V

VTP is negative
Symbols for n channel
Depletion MOSFET
Symbols for p channel
Depletion MOSFET
MOS Capacitor
 MOS Capacitor Under Bias:

Parallel plate capacitor

Accumulation
Positive gate bias
Electrons attracted to gate
 Negative gate bias:
Holes attracted to gate

Depletion Inversion
 MOS Capacitor:
p-type semiconductor

Accumulation Depletion Inversion

 Threshold Voltage
The gate voltage that causes the concentration of
electrons immediately under the gate oxide is equal
to the concentration of holes is called the threshold
voltage.
 NMOS VG = VTN when φs=-φp

where φs- potential at the surface between the Si and SiO2

φp- built in potential on P-substrate
 Before electron
inversion layer is
formed

After electron
inversion layer is
formed
 Ideal V-I characteristics

MOS transistor have three regions of operation

 Cutoff (or) subthreshold region

 Linear (or) nonsaturation region

 Saturation region
  
  
=(Vgs+ Vgs - Vds)/2

=(2 Vgs - Vds)/2

 Linear region

where

If

Then Saturation region

where
Ideal Long channel I-V Characteristics of
nMOSFET
Summary of I-V Relationships
 C-V Characteristics
 Each terminal of an MOS Transistor has capacitance to
the other terminals.
 They are non-linear and voltage dependent
 Parasitic Capacitors
 Not fundamental to the operation of devices but do
impact circuit performance.

 Types:
◦ Diffusion capacitance ( Junction capacitance)
◦ Overlap capacitance ( Oxide related capacitance)
 Diffusion capacitance

 Depends on area, perimeter, depth of

diffusion and doping levels and voltage
 The capacitance depends on both the area and sidewall
perimeter of the source diffusion region
Area AS = WD
Perimeter PS = 2W + 2D

 The total source parasitic capacitance is

Fig. Diffusion region geometry

where Cjbs - the capacitance of the junction between the body

and the bottom of the source.
Cjbssw - the capacitance of the junction between the
body and the side walls of the source
 The area junction capacitance term is

Where CJ - the junction capacitance at zero bias

MJ - the junction grading coefficient, typically in
the range of 0.5 to 0.33
- - the built-in potential that depends on doping
levels
where - the thermal voltage

= kT/q (26 mV at room temperature)

k = 1.380 × 10–23J/K ( Boltzmann’s constant)

T - absolute temperature (300 K at room temp)

q = 1.602 × 10–19 C (charge of an electron )

NA & ND - doping levels of the body and source diffusion region.

ni - intrinsic carrier concentration in undoped Si(1.45 × 1010 cm–3 )

 The sidewall capacitance

 the sidewall capacitance along the nonconductive

trench tends to be minimal, while the sidewall facing
the channel is more significant.
Overlap capacitance
Capacitance of MOS transistor
Cgc versus Vgs
Cgc versus Vds
 CMOS LOGIC
 INVERTER
 NAND GATE
 NOR GATE
Complementary CMOS(static CMOS)
 Complementary CMOS logic gates
◦ nMOS pull-down network
pMOS
◦ pMOS pull-up network pull-up
network
inputs
output

nMOS
pull-down
Pull-up OFF Pull-up ON network
Pull-down Z (float) 1
OFF
Pull-down ON 0 X (crowbar)
 INVERTER

=>

Fig.symbol Fig.Schematic

Truth table
 The NAND gate

=>
Fig.symbols

Fig.Schematic

Truth table
 The NOR gate

=>

Fig.symbols
Fig.Schematic

Truth table
 Stick diagrams
 A stick diagram is a cartoon of a layout.
 Does show all components/vias relative placement.
 Does not show exact placement, transistor sizes,
wire lengths, wire widths, tub boundaries.
 Useful for planning layout
◦ relative placement of transistors
◦ assignment of signals to layers
◦ connections between cells
We represent the different wiring layers with different
colors

Diffusion - green / yellow

Poly - red
Metal1 - blue
Metal2 - purple / orange

Wires on the same layer that touch ALWAYS connect.

There is no way to jumper a wire without changing layers.

Wires on different layers can be cross without connections.

To form connections between different layers you need to
explicitly draw a contact
 Stick Diagrams – Some rules
Rule A

When two or more ‘sticks’ of the same type

cross or touch each other that represents
electrical contact.

48
Rule B

When two or more ‘sticks’ of different type cross or touch each other
there is no electrical contact.
If electrical contact is needed we have to show the connection explicitly

49
Rule C

When a poly crosses diffusion it represents

a transistor.

Note: If a contact is shown then it is not a transistor.

50
 Stick Diagrams for inverter
S
D

VDD D
S
S

D
Vin Vout
D

S
CMOS NAND
A B

Vdd

S S S D D S
D
out
D out
A
S
B D
S D S D
S Gnd

52
 Stick Diagram for CMOS NOR
A B

Vdd
S
A S D
D D S
S
B out
D out
D D
S D D S
S S Gnd
VDD

S D D S S D

S
S D S D S D

54
CMOS Gate Design: 4-input CMOS NOR gate

A
B
C
D
Y

55
 4-input NOR gate
Y=A+B+C+D

VDD
A B C D
A
B
C
Y
D
Y

GND

56
 Layout design rules

 This describes how small features can be and how closely they can be
reliably packed in a particular manufacturing process.
 Industrial design rules are usually specified in microns.
 Universities simplify design by using scalable design rules.
 Mead and Conway popularized scalable design rules based on a single
parameter, λ , that characterizes the resolution of the process.
 λ is generally half of the minimum drawn transistor channel length.
 This length is the distance between the source and drain of a transistor and
is set by the minimum width of a polysilicon wire. For example, a 180 nm
process has a minimum polysilicon width (transistor length) of 0.18 μ m and
uses design rules with λ = 0.09 μ m.
 Designers often describe a process by its feature size. Feature size refers to
minimum transistor length, so λ is half the feature size.
LAYOUT – CMOS INVERTER
Compound Gates
 Compound gates can do any inverting function
 Ex:
A C A C
B D B D
(a) (b)

C D
A B C D
A B
(c)
(d)

C D
A
A B
B
Y Y
C
A C
D
B D
(f)

(e)
Example: O3AI
 Y   A  B  C . D

A
B
C D
Y
D
A B C
Signal Strength
 Strength of signal
◦ How close it approximates ideal voltage source
 VDD and GND rails are strongest 1 and 0
 nMOS pass strong 0
◦ But degraded or weak 1
 pMOS pass strong 1
◦ But degraded or weak 0
 Thus nMOS are best for pull-down network
Pass Transistors
 Transistors can be used as switches
g

s d

s d
Pass Transistors
 Transistors can be used as switches
g g=0 Input g = 1 Output
s d 0 strong 0
s d
g=1 g=1
s d 1 degraded 1

g g=0 Input Output

g=0
s d 0 degraded 0
s d
g=1
g=0
s d strong 1
Fig. Symbol

Fig. Other Symbols

Multiplexers
 2:1 multiplexer chooses between two inputs

S
S D1 D0 Y
0 X 0 0 D0 0
0 X 1 1 Y
D1 1
1 0 X 0
1 1 X 1
Gate-Level Mux Design
 Y  SD1  SD0 (too many transistors)
 How many transistors are needed? 20

D1
S Y
D0

D1 4 2
S 4 2 Y
D0 4 2
2
Transmission Gate Mux
 Nonrestoring mux uses two transmission
gates
◦ Only 4 transistors S

D0
S Y
D1

S
a b
(a)
Beta Ratio Effects
 Nonideal I-V Effects(Second order
effects)
 Velocity saturation
 Mobility degradation
 Channel length modulation
 Threshold voltage effects
 Leakage current
 Temperature Dependence
 Velocity Saturation
 At high lateral field strengths (Vds/L), carrier velocity
ceases to increase linearly with field strength.
 Carriers approach a maximum velocity vsat when high
fields are applied.

where Ec is critical electric field

The slope is the mobility, µeff

where Vc is critical voltage
 Mobility Degradation
 At high vertical field strengths (Vgs /tox), the carriers scatter
off the oxide interface more often, slowing their progess.
 Mobility degradation can be modeled by replacing µ with a
smaller µeff.
 This leads to less current than expected at high Vgs.
 Channel length modulation
 The p–n junction between the drain and body forms a
depletion region with a width Ld that increases with Vdb.
 Higher Vds(assume Vdb ~ Vds) increases the size of the
depletion region around the drain and thus effectively
shortens the channel.
 Channel length modulation is very important to analog
designers because it reduces the gain of amplifiers.
 where VA is called the Early voltage

Fig. Depletion region shortens effective channel length

 Threshold voltage effects
 Increasing the potential between the source and body
raises the threshold through the body effect.
 Increasing the drain voltage lowers the threshold through
drain-induced barrier lowering.
 Increasing the channel length raises the threshold
through the short channel effect.
Body Effect
 When a voltage Vsb is applied between the source and
body, it increases the amount of charge required to invert
the channel. Hence

where Vt0 is the threshold voltage when the source is at

the body potential, φs is the surface potential at threshold,
and γ is the body effect coefficient
Drain-Induced Barrier Lowering
 This drain-induced barrier lowering (DIBL) effect is
especially pronounced in short-channel transistors. It
can be modeled as

where η is the DIBL coefficient, typically on the order of

0.1
 Drain-induced barrier lowering causes Ids to increase
with Vds in saturation.
Short Channel Effect
 The threshold voltage typically increases with channel
length.
 This phenomenon is especially pronounced for small L
where the source and drain depletion regions extend into
a significant portion of the channel, and hence is called
the short channel effect or Vt rolloff
 In some processes, a reverse short channel effect
causes Vt to decrease with length.
 There is also a narrow channel effect in which Vt varies
with channel width.
 Leakage current
 Even when transistors are nominally OFF, they leak small
amounts of current.
◦ Subthreshold Leakage - Subthreshold conduction is caused
by thermal emission of carriers over the potential barrier set
by the threshold
◦ Gate Leakage - a quantum-mechanical effect caused by
tunneling through the extremely thin gate dielectric
◦ Junction leakage is caused by current through the p-n
junction between the source/drain diffusions and the body

Fig.Leakage current paths

 Subthreshold Leakage
 In real transistors, current does not abruptly cut off below
threshold, but rather drops off exponentially.
 When the gate voltage is high, the transistor is strongly ON.

 When the gate falls below Vt, the exponential decline in

current appears as a straight line on the logarithmic scale.

This regime of Vgs <Vt is called weak inversion.
 The subthreshold leakage current increases significantly with
Vds because of drain-induced barrier lowering.
Gate Leakage
 Transistors need high Cox to deliver good ON current, driving
the decrease in oxide thickness. Tunneling current drops
exponentially with the oxide thickness.

Fig. Gate leakage current

Junction leakage

Fig. Substrate to diffusion diodes in CMOS circuits

 The p–n junctions between diffusion and the substrate or

well form diodes.
 The well-to-substrate junction is another diode. The
substrate and well are tied to GND or VDD to ensure
these diodes do not become forward biased in normal
operation.
 However, reverse-biased diodes still conduct a small
amount of current ID.
 Temperature Dependence
 Transistor characteristics are influenced by temperature.
 Carrier mobility decreases with temperature

where T is the absolute temperature, Tr is room temperature, and kμ is a

fitting parameter with a typical value of about 1.5
 At high Vgs, the current has a negative temperature
coefficient; i.e., it decreases with temperature.
 At low Vgs, the current has a positive temperature coefficient.
 Thus, OFF current increases with temperature. ON current
Idsat normally decreases with temperature.
Fig. I–V characteristics of nMOS transistor in Fig. Idsat vs. temperature
saturation at various temperatures
 circuit performance can be improved by cooling.
 Most systems use natural convection or fans in
conjunction with heat sinks, but water cooling, thin-film
refrigerators, or even liquid nitrogen can increase
performance if the expense is justified.
 RC delay model
 This approximates the nonlinear transistor I-V and C-V
characteristics with an average resistance and capacitance
over the switching range of the gate.

 Effective Resistance :- a transistor is treated as a switch in

series with a resistor.
 The effective resistance is the ratio of Vds to Ids averaged
across the switching interval of interest.
 An nMOS transistor of k times unit width has resistance R/k.
A unit pMOS transistor has greater resistance, generally in
the range of 2R–3R, because of its lower mobility.
 According to the long-channel model, current decreases
linearly with channel length and hence resistance is
proportional to L.

 Gate and Diffusion Capacitance :- C to be the gate

capacitance of a unit transistor
 A transistor of k times unit width has capacitance kC.
Diffusion capacitance depends on the size of the
source/drain region.
 Increasing channel length increases gate capacitance
proportionally but does not affect diffusion capacitance.
Equivalent RC Circuits

Fig. Equivalent circuits for transistors

Fig. Equivalent circuit for an unit inverter
Example : Sketch a 3-input NAND gate with transistor widths chosen
to achieve effective rise and fall resistance equal to that of a unit
inverter (R). Annotate the gate with its gate and diffusion capacitances.
Assume all diffusion nodes are contacted. Then sketch equivalent
circuits for the falling output transition and for the worst-case rising
output transition.

Fig. 3-input NAND gate

Fig. 3-input NAND gate with capacitances
Fig. simplified 3-input NAND gate with capacitances

Fig. Equivalent circuits for a 3-input NAND gate

 Elmore Delay model
 Circuits can be represented as an RC tree.
 The root of the tree is the voltage source and the leaves
are the capacitors at the ends of the branches.
 Elmore delay is the sum over each node in the tree of
the resistance Ris between the node i and source s,
multiplied by the capacitance of the node.
Example: Estimate tpd for a unit inverter
driving m identical unit inverters
Repeat Previous Example if the driver
is w times unit size.
 Linear Delay Model
 In this model delay is a linear function of the fanout of a gate

where p is the parasitic delay inherent to the gate when no

load is attached and f is the effort delay(stage effort) that
depends on the complexity and fanout of the gate

 The complexity is represented by the logical effort, g

 A gate driving h identical copies of itself is said to have a
fanout or electrical effort of h.

where Cout is the capacitance of the external load being

driven and Cin is the input capacitance of the gate.
 Logical Effort
 It is the ratio of the input capacitance of the gate to the
input capacitance of an inverter that can deliver the
same output current.

Fig. Logic gates sized for unit resistance

 Parasitic Delay
 The parasitic delay of a gate is the delay of the gate
when it drives zero load.
 It counts only diffusion capacitance on the output node.
 The inverter has three units of diffusion capacitance on
the output, so the parasitic delay is 3RC .(pinv is the ratio
of diffusion capacitance to gate capacitance)

Fig. n-input NAND gate parasitic delay

 Delay in a Logic Gate
 Example: Use the linear delay model to estimate the
delay of the fanout-of-4 (FO4) inverter. Assume the
inverter is constructed in a 65 nm process with Ꞇ=3ps

 The logical effort of the inverter is g= 1.

 The electrical effort (h) is 4 because the load is four
gates of equal size.
 The parasitic delay of an inverter is pinv ~ 1.
 The total delay is d = gh + p = 1 × 4 + 1 = 5 in
normalized terms, or tpd = 15 ps in absolute terms