During positive half cycle of input voltage, TI is forward biased. At ωt = α
TI is triggered and i0 = iT1 starts building up through the load. At π, load and source voltages are zero but the current is not zero because of the presence of inductance in the load circuit. At β > π, load current reduces to zero. After π, TI is reverse biased but does not turn off because i0 is not zero. At β only,
when i0 is zero, TI is turned off as it is already reverse biased.
v0 0 vT 1 vs From β to π + α, no current exists in the power circuit, therefore vT 2 vs During negative half cycle of input voltage, T2 is turned on at π + α > β, current i0 = iT2 starts building up in the reversed direction through the load.
At 2π, vs and v0 are zero but i0 is not zero.
At π + α + γ , iT2 = i0 = 0 and T2 is turned off because it is already reverse biased.
v0 0 From v πv + αv+ γ to2π v + α , no current exists in the power circuit, therefore, T1 s T2 s 1/ 2 1 Vm 1 sin 2 sin 2 2 2 V0( rms ) Vm sin td t 2 2 2 Gating signal requirements • For R load, thyristor Tl stops conducting (natural commutation)at ωt = π • T2 is now forward biased after π. When T2 is triggered at π + α, it gets turned on since it is already forward biased by source voltage. • Thus pulse gating is suitable for R load as shown below Fig. 1 Single phase AC voltage controller –RL load • Pulse gating is not suitable for RL loads with (with pulse gating) α<φ • At ωt = α, T1 is fired and the current starts flowing. Due to the nature of inductive load, the current will not come to zero at π. It becomes zero only at β = α + γ •At π +α, T2 is fired. As T1 is still conducting, voltage drop across T1 reverse biases T2 and hence T2 is not turned on at π + α • At α + γ , current decays to zero and T1 stops conducting. So that T2 gets forward biased. Fig. 2 Types of gating signals • If pulse gating is used, gate pulse is with drawn before α + γ . So T2 does not get turned on. •If continuous gating is used, the pulse is available at α + γ . Hence T2 is fired •In practice continuous gating is undesirable as it leads to more heating of the SCR gate and it increases the size of the pulse transformer. • This difficulty can be overcome by applying train of pulses or high frequency carrier gating References 1. Bimbhra, P.S. Power Electronics. Khanna Publishers, New Delhi, 5thEdition, 2012.