Design import

 RTL Verilog File

• Gate level RTL Synthesis

 LEF Files: Library Exchange Format:

contains
• -Technology library: process information:
eg: layers, design rules, cap/res values etc
- Core library: core standard cells,
- IO library ( contains IO cells)

 MMMC File : Multi Mode Multi Corner

• Contains:
• - Library sets (timing), RC corner
(min/max) operating conditions, delay
corners, analysis views