Parallel Fault Simulation Using Verilog PLI

Sara Karamati
CAD Lab, Department of electrical and computer engineering, university of Tehran

Outline
Fault Simulation y Parallel Fault Simulation y Parallelism Implementation y Parallel Fault Injection & Removal y A Case Study y Speed Up Analysis y Conclusion
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Fault Simulation
Fault collapsing y For all faults
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Fault injection Simulation in presence of faults Fault removal

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Fault coverage

Parallel Fault Simulation

Collapse faults based on DUT y Provide Nf circuits, working in parallel ?!?! y While there is a fault
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Inject Nf faults into Nf circuits ?!?! Simulate all Nf circuits simultaneously ?!?! Compare golden model with Nf faulty circuits Remove Nf faults
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Coverage factor
4

Several techniques for reducing fault simulation time

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The multiprocessor Fault Simulation Techniques[1]-[4].

Test set partitioning Fault list partitioning Circuit partitioning

y y

Parallel Fault Simulation Method Based on Structurally Synthesized BDDs (SSBDD) [8]. Hierarchical Parallel Fault Simulation Method [10]

Parallel Fault Simulation Engine Problems

Specific Simulation Engines y Several Workstations y Unfamiliar from Designers Point of View y No Integration of HDL & Fault Simulation
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Specific Simulation Engine COST

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Who Says There is no free lunch?

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PLI Approach
No Specific Simulation Engine Utilization of RTL CAD Tools HDL & Fault Simulation Integration The Same Steps as Serial Fault Simulation Its Free, Why not use it?

Parallelism Implementation
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Trivial solution
Generate Nf real circuits, using generate statement Lots of PLI & tracing

More realizable solution

Pack Nf inputs of all Nf circuits into a vector One single circuit, with vectorized inputs A vectorizable library of components

Trivial Solution
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Generation of ordinary DUT

More Realizable Solution

y

New Configured DUT

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Configurable Components
module and_n #(parameter n = 2, tphl = 1, tplh = 1, nf=3) (out,in); input [(n*nf)-1:0] in; output [nf-1:0]out; reg [nf-1:0]val; integer i; always@(in) begin val = in[nf-1:0]; for(i=1; i<n; i=i+1) begin val=val & in[(nf*i)+:nf]; end end assign out=val; endmodule
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Parallel Fault Injection

Read Nf fault strings from fault list y While (counter < Nf)
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Modify each string in order to match the vectorized circuit

x char * str_modifier ()

Inject modified fault into vectorized circuit

x ParInjectFault ()

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Parallel Fault Removal

y

While (counter < Nf)

Modify each string in order to match the vectorized circuit
x char * str_modifier ()

Remove modified fault from vectorized circuit

x ParRemoveFault ()

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Parallel Circuit Simulation

Simulate vectorized circuit y Nothing more !!!
y

Different bits of the inputs instead of inputs to different simulation runs Different bits of the outputs instead of outputs of different simulation runs

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A Sample Parallel Fault Simulation

The c499 Benchmark as DUT y Fanout Insertion via New Components y 50 Parallel Faults, i.e. Nf =50 y Some Modifications to Testbench y ParFaultInjection.dll y Faster Simulation
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C499 Parallel Fault Simulation

module c499PSF #(parameter nf = 50); integer status[nf-1:0]; reg [nf-1:0] stuckAtVal; reg [500:0] wireName [nf-1:0]; wire [nf-1:0]N724G,N725G,N726G,N727G, c499_fo #(nf)FUT(N1,N5,N9,N13,N17,N21, $ParInjectFault (nf, wireName[0], wireName[1], , wireName[50], stuckAtVal[0], stuckAtVal[1], , stuckAtVal[50]); $ParRemoveFault( nf, wireName[0] , wireName[1], , wireName[50]);

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Speed Up vs. Nf
4 3.5 3 2.5 2 1.5 1 0.5 0 Nf = 1 Nf = 5 Nf = 10 Nf = 20 Nf = 30 Nf = 50
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Speed Up

Speed Up for ISCAS Benchmarks Nf=50

Speed Up
3.5 3 2.5 2 1.5 1 0.5 0 C432 C444 C499 C1355 C6288 S298 S713 S832
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Speed Up

Conclusion
Fault Simulation Significance y Parallel Fault Simulation Engine, a Drawback y PLI Approach as a Free Lunch y Simulate Nf Circuits in Parallel y Parallelism via Vectorized Circuit y Inject & remove Nf Faults y Speed up Saturation over Nf y Speed up Analysis for ISCAS Benchmarks
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References
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[1] D. Krishnaswamy, E.M. Rudnick, J.H. Patel and P.

Banejee, " SPITFIRE: scalable parallel algorithms for test set partitioned fault simulation," in Proc. VLSI Test Symposium 1997. [2] M. B. Amin and B.Vinnakota, Data Parallel-Fault Simulation, in IEEE Trans.VLSI Systems, vol. 7, no. 2, pp. 183-190, Jun. 1999. [3] Amit K.Varshney, Eric Skuldt, High Performance Parallel Fault Simulation, Proceedings of the International Conference on Computer Design:VLSI in Computers & Processors, 2001. [4] Steven Parkes, Prithviraj Banerjee, Janak Patel, A Parallel Algorithm for Fault Simulation based on PROOFS, International Conference on Computer Design, 1995. [5] Raja Daoud, Fuson Ozguner, Highly Vectorizable Fault Simulation on the Cray XMP Supercomputer, IEEE Transactions on Computer-Aided Design, December 1989. [6] S. Seshu, On an improved diagnosis program, IEEE Transactions on Electronic Computers, vol. 14, pp. 7679, 1965.

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References
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[7] M. Nadjarbashi, Z. Navabi and M. R. Movahedin, Line Oriented Structural Equivalence Fault Collapsing Proceedings of Workshop on Model and Test, Germany, 2000. [8] R. Ubar, S. Devadze, J. Raik and A. Jutman, Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs, 12th IEEE European Test Symposium (ETS), 20-24 May 2007, pp. 131 136.

[9] H. Kyunghwan and L. Soo-Young, A parallel implementation of fault simulation on a cluster of workstations, IEEE International Symposium on Parallel and Distributed Processing, 14-18 April 2008, pp. 1-8. [10] S. Misera and H. T.Vierhaus, FIT - A Parallel Hierarchical Fault Simulation Environment, IEEE International Conference on Parallel Computing in Electrical Engineering (PARELEC), 7-10 Sept. 2004, pp. 289-294.

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Specific Simulation Engine vs. PLI Approach Cont.

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