Implementation of High-Speed and Area-Efficient VLSI

Architecture of three-operand Binary Adder

Presented by (Batch No :18)

18FE1A0499 - P. Rizwana
18FE1A0487 - N. Tejaswini
18FE1A0463 - K. Yoga Sriram
18FE1A0493 - P. Sri Harsha

Under the Guidance of

Dr. Venkata Kishore Perla

Department of Electronics and Communication Engineering

Contents
• Objective
• Existing Methods
• Limitations in existing Methods
• Proposed Adder
• RTL and simulation waveforms
• Applications
• Logic used in Algorithms
• Results
• Requirements
Objective
• Three-operand binary adder is the basic fundamental unit to
perform modular arithmetic in various cryptography and
Pseudo-Random Bit Generator.
• To achieve optimal system performance while maintaining
physical security it is necessary to implement cryptography
algorithms on hardware.
Existing Methods
Carry Save 3-Operand Adder
Carry Save 3-Operand Adder

• Carry Save three-operand binary Adder(CS3A) is the area efficient

and widely adopted technology to perform three-operand binary
addition in the modular arithmetic used in cryptography.

• However the longer carry propagation in ripple carry stage of CS3A

seriously influence the performance of Adder
Han Carlson 3-Operand Adder
HC3A
• In order to shorten the critical path delay a parallel prefixed Han-
Carlson Adder(HCA) can be used for three-operand binary adder.
• Though it reduces path delay it increases the area.
• So in order to reduce path delay and area occupancy, there is a need
for proposed three operand binary adder.
Proposed VLSI architecture of three-
operand Binary Adder
 The proposed adder technique is a parallel prefix adder with four
stages.
 It consists of bit addition logic, base logic, propagate and generate
logic(PG) and sum logic
• Third stage is the combination of black cell and grey cell.
CS3A RTL
HC3A RTL
Proposed Adder RTL

Proposed Adder RTL

CS3A

HC3A
Simulation Waveform of Proposed Adder

Proposed Adder Simulation Waveform

Applications
Modified Dual Combined Linear Congruential
Generator (MDCLCG).

• A MDCLCG is a pseudo-random number generator algorithm based

on combining two or more linear congruential generators.
Architecture of MDCLCG
LCG
Logic of MDCLCG
• Considering multiplier constants as a1, a2, a3, a4 and increment constants as b1,b2,
b3,b4 for 32 bit MDCLCG.
• Let initial seeds : (x0,y0,p0,q0).
• Generalized formula for LCG-> Xi=(Ai*X(i-1)+Bi) mod 2^n.
where n= Number of bits.
• The sequences are computed as follows:
Xi={x1,x2,x3,x4,…}
Yi={y1,y2,y3,y4,…}
Pi={p1,p2,p3,p4,…}
Qi={q1,q2,q3,q4,…}
• The sequences Bi and Ci are in the MDCLCG architecture are
generated by comparing Xi with Yi and Pi with Qi respectively using
magnitude Comparator.
• Finally, the pseudorandom bit Zi is generated by Bi XOR Ci.
Simulation Waveform of MDCLCG
Results
Adder Delay (n sec) Area (LUT)
CS3A 21.032 33
HC3A 17.854 100
Proposed Adder 12.128 66
Results of MDCLCG
MDCLCG Delay (n sec) Area (LUT)
using
CS3A 89.170 3413
HC3A 80.395 5333
Proposed Adder 71.163 4533
Requirements

• Tool : Xilinx 14.7

• VERILOG coding style is used.