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BLOCK DIAGRAM:
AVR MICROCONTROLLER: The AVR is a Modified Harvard architecture machine with program and data stored in separate physical memory systems that appear in different address spaces but having the ability to read data items from program memory using special instructions. AT MEGA 128: The ATmega128 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega128 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
FEATURES OF AVR: RISC / Harvard Powerful microcontroller designed for small applications Very low power operation 118 instructions 1 instruction per clock cycle (pipelined) Register-to-register operation RISC core with ~100 instructions Modest clock speeds (4-16 MHz) 8-bit bus, 32 GP 8-bit registers Intended as single chip solutions In-circuit programmable Flash(~1000 cycles) Small amount of EEPROM and SRAM Single-cycle execution of most instructions Several on-chip peripherals (UART, SPI,TWI, ADC, PWM, WDT..)
FEATURES OF OV 6620:
101,376 pixels, 1/4 lens. Small size-40x28mm Data format - RGB Raw Data. 8/16 bit video data. Wide dynamic range. Anti-blooming. White balance control. Single 5-Volt supply, low power dissipation. Lens-4.9mm. Array size-176x144 Signal to noise ratio-48db I2C interface. Image enhancement - brightness, contrast, saturation, sharpness.
2-wire serial bus Serial data (SDA) and Serial clock (SCL) Half-duplex, synchronous, multi-master bus No chip select or arbitration logic required Lines pulled high via resistors, pulled down via open-drain drivers (wired-AND)
I2C Protocol
1. Master sends start condition (S) and controls the clock signal 2. Master sends a unique 7-bit slave device address 3. Master sends read/write bit (R/W) 0 - slave receive, 1 - slave transmit 4. Receiver sends acknowledge bit (ACK) 5. Transmitter (slave or master) transmits 1 byte of data
6. Receiver issues an ACK bit for the byte received 7. Repeat 5 and 6 if more bytes need to be transmitted. 8.a) For write transaction (master transmitting), master issues stop condition (P) after last byte of data. 8.b) For read transaction (master receiving), master does not acknowledge final byte, just issues stop condition (P) to tell the slave the transmission is done
TWI Registers
TWBR (bit rate register) -Controls the period of SCL when the TWI module is operating in Master mode. TWAR (address register) -Used when TWI module is receiving data to identify its address. TWCR (control register) -Controls operation of the TWI unit -Used to generate START, STOP, ACK pulse -Also enables TWI operation including interrupt enables TWSR (status register) -Reflects the status of the TWI logic bus via codes. -Holds the prescale value for the TWI SCL pulse generator TWDR (data register) -In transmit mode, it holds the data to send -In receive mode, it holds the data received
USART
Universal Synchronous and Asynchronous serial Receiver and Transmitter A standard I/O device that provides conversions between serial and parallel data Provides a basic protocol for serial communication Speed, framing, error control USART ON AVR (ATMega128) USART - The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device
Features: Full Duplex Operation (Independent Serial Receive and Transmit Registers) Asynchronous or Synchronous Operation Master or Slave Clocked Synchronous Operation High Resolution Baud Rate Generator Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits Odd or Even Parity Generation and Parity Check Supported by Hardware Data Overrun Detection Framing Error Detection Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
Three Separate Interrupts on TX Complete, TX Data Register Empty, and RX Complete Multi-processor Communication Mode Double Speed Asynchronous Communication Mode
USART Initialization: The USART has to be initialized before any communication can take place. The initialization process normally consists of setting the baud rate, setting frame format and enabling the Transmitter or the Receiver depending on the usage. For interrupt driven USART operation, the global interrupt flag should be cleared (and interrupts globally disabled)
IMAGE PROCESSING: A method for adjusting the color reproduction of a color image composed of pixels provided in a plurality of color channels is based on generating a reference image from a combination of the color channels, whereby each spatial coordinate of the reference image is characterized by a reference image level. A method for processing Bayer images method comprising: Receiving a raw image from a sensor with Bayer color arrays. Determining a corresponding dot in the raw image that corresponds to each pixel in a final image. Locating color reference pixels in the raw image according to the corresponding dot. Selecting interpolation pixels in the raw image according to the color reference pixels and interpolating color values of the each pixel in the final image according to color values of the interpolation pixels.
BAYER FORMAT: Color filters used in most single-chip digital image sensors used in digital cameras, camcorders, and scanners to create a color image. The filter pattern is 50% green, 25% red and 25% blue, hence is also called RGBG or GRGB. This Bayer format is processed in MATLAB to obtain true RGB picture.
To create a full color image, the camera's image processor calculates, or interpolates, the actual color of each pixel by looking at the brightness of the colors recorded by it and others around it.