Testable SRAM Design using March-Y Algorithm

G. Rajesh Kumar 08A21D5712

Project Overview

Design For Testability SRAM Memory Testing BIST March-Y Algorithm

What is this project about?

Design a BIST architecture to test SRAM Focus on
o

Algorithmic solution proposed to design a BIST architecture for testability in SRAM chip

Timeline

FAULT MODELS AND DEFINITIONS

Faults modeled from the memory defects can be summarized as follows:

Stuck-at-Fault (SF): Either a cell or a line is stuck to logical `0' or `1'. Transition Fault (TF): the 0!1 (or 1!0) transition is impossible on a cell or a line. Coupling Fault (CF): When a cell is written to 0!1 (or 1!0), the content of the other cell is changed. Address Decoder Fault (ADF): No cell will be accessed with a certain address or multiple cells are accessed simultaneously or a certain cell can be accessed with multiple addresses.

Retention Faults(RF) : A cell fails to retain its logic value after some time

Built-In Self-Test (BIST)

A built-in self-test (BIST) or built-in test (BIT) is a mechanism that permits a machine to test itself. Engineers design BISTs to meet requirements such as:
o

high reliability lower repair cycle times

or constraints such as:

o

limited technician accessibility cost of testing during manufacture

Block Diagram

Finish

Operation

The FSM should have a START state and be activated by an external signal RUN_BIST. The design should have an input signal BIST_COMP feedback from the SRAM such that when BIST_COMP=1 means there is a fault, 0 no fault. If BISTCOMP=1, the simulation should be terminated and the FSM goes to END state. The address lines should read the failing address.

Output pins Read_En to be activated during the Read operation, and Write_En to be activated during the write operation. A Compare state follows each Read operation, during which NO Read or Write operations are activated An output signal called Error is activated when the FSM goes to END state corresponding to failure.

Traditional Method for SRAM Testing

March-X Algorithm

{ (w0) (r0,w1,r1,w1,r1) (r1,w0,r0,w0,r0) (r0,w1,r1,w1,r1) (r1,w0,r0,w0,r0) (r0)}

The basic notations used in algorithm are as follows:

o o o o o o o

: address 0 to n-1 : address n-1 to 0 : either way w0: Write 0 to the word w1: Write 1 to the word r0: Read a cell whose value should be 0 r1: Read a cell whose value should be 1

Proposed Method
March-Y Algorithm

March Y Algorithm

(W0); (R0,W1,R1); (R1,W0,R0); (R0)

The basic notations used in algorithm are as follows:

o

: address 0 to n-1 : address n-1 to 0 : either way W0: Write 0 to the word W1: Write 1 to the word R0: Read a cell whose value should be 0 R1: Read a cell whose value should be 1

11

March-Y Algorithm

March-Y(R, C) { /*--- step 1: write 0 to each cell ---*/ foreach_row(i=0; i<R; i++){ foreach_col(j=0; j<C; j++){ Write 0 to cell(i, j); } } /*--- step 2: change each cell from 0 to 1 in a forward manner ---*/ foreach_row(i=0; i<R; i++){ foreach_col(j=0; j<C; j++){ Read 0 from cell(i, j); Write 1 to cell(i, j); Read 1 from cell(i, j) } } /*--- step 3: change each cell from 1 to 0 in a backward manner ---*/ foreach_row(i=(R-1); i>=0; i--){ foreach_col(j=(C-1); j>=0; j--){ Read 1 from cell(i, j); Write 0 to cell(i, j); Read 0 from cell(i, j) } } /*--- step 4: read 0 to each cell ---*/ foreach_row(i=0; i<R; i++){ foreach_col(j=0; j<C; j++){ Read 0 from cell(i, j); } }

March-Y Algorithm

Design Methodology

14

Verilog Module Hierarchy

15

March-Y Algorithm
Procedure

SRAM

March-Y Algorithm
(W0); (R0,W1,R1); (R1,W0,R0); (R0)

00 01 02 03 04 05 06 07 08 09 10 11 .. .. .. 31

00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000

SRAM

March-Y Algorithm
(W0); (R0,W1,R1); (R1,W0,R0); (R0)

00 01 02 03 04 05 06 07

00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111

Compare 00000000 Temp. Reg.

08 09 10 11 .. .. .. 31

SRAM

March-Y Algorithm
(W0); (R0,W1,R1); (R1,W0,R0); (R0)

00 01 02 03 04 05 06 07 08 09 10 11 .. .. .. 31

00000000 00000000 00000000 00000000 00000000 00000000 00000000 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111

SRAM

March-Y Algorithm
(W0); (R0,W1,R1); (R1,W0,R0); (R0)

00 01 02 03 04 05 06 07

00000000 00000000 00000000 00000000 00000000 00000000 00000000 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111

Compare 11111111 Temp. Reg.

08 09 10 11 .. .. .. 31

Faulty Chip

if(WE==1 && RE==0) begin if(address==15) else RAM[address]=data_write; end if(WE==0 && RE==1) begin // if(address==25) // // else data_read= RAM[address]; end //error injected at location 25 data_read=8'b11111010; //error injected at location 15 RAM[address]=8'b10101010;

SRAM

March-Y Algorithm
(W0); (R0,W1,R1); (R1,W0,R0); (R0)

00 01 02 03 .. .. .. 15

00000000 00000000 00000000 00000000 00000000 00000000 00000000 10101010 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111

Compare 00000000 Temp. Reg.

.. .. .. .. .. .. .. 31

Results

Results

Faulty Chip

if(WE==1 && RE==0) begin if(address==15) else RAM[address]=data_write; end if(WE==0 && RE==1) begin // if(address==25) // // else data_read= RAM[address]; end //error injected at location 25 data_read=8'b11111010; //error injected at location 15 RAM[address]=8'b10101010;

Results

Results

Conclusion

Computation Time is less

o

March-X -------------- Nearly 0.9ns March-Y -------------- Less than 0.08ns

Less number of Computation steps Low Power Testing 100% Fault Coverage Compared to March -X

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Presented by G. RAJESH KUMAR (08A21D5712)

M. Tech. (VLSI SYSTEM DESIGN)