THE MIMD

(MULTIPLE INSTRUCTION AND MULTIPLE

DATA)
Cabuag, Kenji
Mosquete, Aeryk John
Pulmano, Rheyster Vince
AGENDA
• Classification of Computer Architecture
• Computer System Architecture and
Components
• Architecture Failures
CLASSIFICATION
OF COMPUTER
ARCHITECTURE
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MIMD
ARCHITECTURE
• MIMD stands for Multiple-instruction multiple-data streams. It
includes parallel architectures are made of multiple processors and
multiple memory modules linked via some interconnection network.
They fall into two broad types including shared memory or message
passing.
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EXAMPLE OF MIMD
AMD RYZEN 7 1700

• This processor has 8 cores and 16 threads which it can processed multiple
data and instruction one at a time.
• This processor has the speed of 3.0 GHZ up to 3.7 GHZ.
• One of the latest processor made by AMD and it was released last 2017.
• This processor uses the AMD "Zen" Core Architecture that improves energy
efficiency, higher clock speeds and more cores than ever before.
 COMPUTER
SYSTEMS
ARCHITECTURE
COMPONENTS
THE ZEN 7

ARCHITECTURE
• The Zen is based on the 14nm FinFET node
• Zen Microarchitecture
• Has Op instructions
• 4 Integer Units
• 2 Load/Store Units
• 72 out of order Loads
• 2 Floating Point Units
• Each core has 2 threads
• The basic Zen complex comprises of 4 cores and an
L3 cache.
• All cores can access the cache blocks with the same
average speed.
CPU COMPLEX 8

• A CPU complex (CCX) is four cores

connected to an L3 Cache
• The L3 Cache is a 16-way associative,
8MB, mostly exclusive of L2.
• The L3 cache is made of 4 slices, by low-
order address interleave
• The large Op cache helps improve
throughput and latency time.
• Each Zen core has 6 pipes
• 4 ALUs (Arithmetic Logic Units)
• 2 AGUs (Address Generation Units)
• These AGUs can perform two 16-byte
loads per cycle
ZEN WITH SMT 9

• The best feature of Zen is the SMT

(Simultaneous Multi-Threading)

• The SMT increases throughput by

executing two threads at the same time.

• The virtual threads are independent cores

to softwares and this allows more
executions.
LOAD/STORE AND L2 10

• The cache hierarchy consist of a fast private L2

and a large fast shared L3.

• This enables faster band width for prefetch

improvements allowing faster cache-to-cache
transfers.

• The entire systems adds up to faster L1, L2 and

L3 caches that offer faster load

• Bandwidth is improved to almost 2x on L1 and

L2 while L3 cache system bandwidth is
improved by 5x.
ARCHITECTURE
FAILURES
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ARCHITECTURE
FAILURES OF MIMD
• Extra Cost
• Better Cooling
• Power Consumption
• Lack of Scalability
• Load Balancing Problem
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REFERENCES
• https://learnlearn.uk/alevelcs/sisd-simd-misd-mimd/
• https://wccftech.com/amd-zen-architetcure-details/
THANK YOU