THE 8051

I/O PORTS, PINS &

CIRCUITS
I/O PORTS
The 8051 has 4 bidirectional 8-bit I/O ports.
Each port is connected to an 8-bit register in the SFR.
P0 = 80H, P1 = 90H, P2 = A0H, P3 = B0H
Each port is also connected to an output driver and an input
buffer.

Some of the 4 ports have uses in addition to simple I/O.

Ports P0 and P2 as the 8051’s Address and Data busses.
Port P3 as the 8051’s external control lines for the timers and
counters etc.

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ALL INPUT OR ALL OUTPUT?
Do these ports operate only as 8-bit input or 8-bit output
ports?
NO.
The individual bits of each port can be operated as either input
or output.

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PORT P1
Can be used both for input and output.
Its pins are connected to internal pull-up resistors
so no external pull-up is needed.
Therefore, if the external pin is left un-connected, the matching
bit will be read as a logic high.

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INTERNAL STRUCTURE OF A PIN OF PORT 1

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INTERNAL STRUCTURE OF A PIN OF PORT 1
Each pin of I/O ports
Internal CPU bus: communicate with CPU
A D latch store the value of this pin
D latch is controlled by “Write to latch”
– Write to latch: write data into the D latch
2 Tri-state buffer
TB1: controlled by “Read pin”
– Read pin: really read the data present at the pin
TB2: controlled by “Read latch”
– Read latch: read value from internal latch

A transistor M1 gate
Gate = 0: open
Gate = 1: close
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TRI-STATE BUFFER

Output Input

Tri-state control
(active high)

L L H H Low

H H Highimpedance
(open-circuit)

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 READ VC
L AT C H TB2 C
LOAD(L
1)
INTERNAL D Q P1.X
CPU BUS P1.X PIN

WRITE TO CLK Q M1
L AT C H

TB1
READ PIN

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WRITING “1” TO OUTPUT PIN P1.X

READ VC
L AT C H TB2 C
L O A D ( L 2. output pin is
1. write a 1 to the pin 1) Vcc
D Q
1 P1.X
INTERNAL
CPU BUS P1.X PIN
0 output ‘1’
WRITE TO CLK Q M1
L AT C H

TB1
READ PIN

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WRITING “0” TO OUTPUT PIN P1.X

READ VC
L AT C H TB2 C
LOAD(L 2. Output pin
1) is ground
1. write a 0 to the pin
INTERNAL D Q 0 P1.X
CPU BUS P1.X PIN

CLK Q 1 M1 Output ‘0’

WRITE TO
L AT C H

TB1
READ PIN

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PORT 1 AS OUTPUT [WRITE TO A PORT]
Let P1 toggle.
MOV A , #55H
BACK: MOV P1 , A
ACALL DELAY
CPL A
SJMP BACK
Let P1.0 toggle.
BACK: SET P1.0
ACALL DELAY
CLR P1.0
ACALL DELAY
SJMP BACK

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READING “HIGH” AT INPUT PIN

READ VC 2. MOV A,P1

L AT C H TB2 C
1. write a 1 to the pin LOAD(L external pin =
MOV P1,#0FFH 1) ‘HIGH’
INTERNAL D Q 1 1 P1.X
CPU BUS P1.X PIN

CLK Q 0 M1
WRITE TO
L AT C H

TB1
READ PIN
3. Read pin=1, Read latch=0, Write to latch=1

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READING “LOW” AT INPUT PIN

READ VC
L AT C H TB2 C 2. MOV A,P1
1. write a 1 to the pin L O A D ( L External pin =
MOV P1,#0FFH 1) ‘LOW’
D Q
1 P1.X
INTERNAL
CPU BUS P1.X PIN

CLK Q 0 M1
WRITE TO
L AT C H

TB1
READ PIN
3. Read pin=1 Read latch=0 Write to latch=1

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PORT 1 AS INPUT [READ FROM PORT]

In order to make P1 an input, the port must be

programmed by writing 1 to all the bit.
MOV A,#0FFH ;A=11111111B

MOV P1,A ;make P1 an input port

BACK: MOV A,P1 ;get data from P1

MOV P2,A ;send data to P2

SJMP BACK
To be an input port, P0, P1, P2 and P3 have similar methods.

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INSTRUCTIONS FOR READING AN INPUT
PORT PIN
Following are instructions for reading external pins of ports:

Mnemonics Example Description

MOV A , PX MOV A , P2 Bring into A the data at port pin P2

JNB PX.Y , …. JNB P2.1 , TARGET Jump if pin P2.1 is Low

JB PX.Y , …. JB P2.1 , TARGET Jump if pin P1.3 is High

MOV C, PX.Y MOV C , P2.4 Copy status of pin P2.4 to Carry

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READING THE LATCH

1. Read pin=0 Read latch=1 Write to latch=0

(Assume P1.X=0 initially)
READ VC
L AT C H TB2 C
LOAD(L
2. CPU compute 0 1) 4. P1.X=1
P1.X OR 1
0 1
I N‘1’
TERNAL D Q P1.X
CPU BUS P1.X PIN
WRITE TO CLK Q 0 M1
L AT C H
3. write result to latch
Read pin=0,
Read latch=0
Write to latch=1 TB1
READ PIN

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READING LATCH
Exclusive-or the Port 1
MOV P1,#55H ;P1=01010101
ORL P1,#0F0H ;P1=11110101
1. The read latch activates TB2 and bring the data from the Q latch
into CPU.
Read P1.0=0
2. CPU performs an operation.
This data is ORed with bit 1 of register A. Get 1.
3. The latch is modified.
D latch of P1.0 has value 1.
4. The result is written to the external pin.
External pin (pin 1: P1.0) has value 1.
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READING INPUT VS. PORT LATCH
When reading ports, there are two possibilities
Read the status of the input pin. From external pin value
MOV A, PX
JNB P2.1, TARGET ; jump if P2.1 is not set
JB P2.1, TARGET ; jump if P2.1 is set

Read the internal latch of the output port.

ANL P1, A ; P1 ← P1 AND A
ORL P1, A ; P1 ← P1 OR A
INC P1 ; increase P1

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READ-MODIFY-WRITE INSTRUCTIONS

This features combines 3 actions in a single instruction.

1. CPU reads the latch of the port

2. CPU perform the operation

3. Modifying the latch

4. Writing to the pin

Note that 8 pins of P1 work independently.

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PORT 1 AS INPUT [READ FROM LATCH]

Exclusive-or the Port 1

MOV P1 , #55H ;P1=01010101
AGAIN: XOR P1 , #0FFH ;complement
ACALL DELAY
SJMP AGAIN
Note that the XOR of 55H and FFH gives AAH.
XOR of AAH and FFH gives 55H.
The instruction read the data in the latch (not from the pin).
The instruction result will put into the latch and the pin.

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READ-MODIFY-WRITE INSTRUCTIONS
Mnemonics Example
ANL ANL P1,A
ORL ORL P1,A
XRL XRL P1,A
JBC PX.Y, TARGET JBC P1.1,TARGET
CPL CPL P1.2
INC INC P1
DEC DEC P1
DJNZ PX, TARGET DJNZ P1,TARGET
MOV PX.Y,C MOV P1.2,C
CLR PX.Y CLR P1.3
SETB PX.Y SETB P1.4

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PORT P0

P0 can be used for input or output.

The pins of P0 are connected internally to an “open drain”
circuit (similar to open collector but using MOS transistors).
Therefore, it must be connected to an external pull-up resistor (10
KW) to operate properly as an output port.

To operate P0 as an input port, it must be programmed by

writing 1’s to all of its bits.
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INTERNAL STRUCTURE OF A PIN OF PORT 0

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INTERNAL STRUCTURE OF A PIN OF PORT 0
A D D R / D ATA C O N T R OVLC C
0
M2
READ
L AT C H TB2

P0.X
PIN
INTERNAL D Q
CPU BUS P0.X M1
WRITE TO CLK Q
L AT C H

TB1
READ PIN

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WRITE ADDRESS/DATA = “1” TO PORT 0
A D D R / D ATA C O N T R OVLC C
1 1
1 M2
READ
L AT C H TB2

P0.X
0 P I N1
INTERNAL D Q
CPU BUS P0.X M1
WRITE TO CLK Q
L AT C H

TB1
READ PIN

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WRITE ADDRESS/DATA = “0” TO PORT 0
A D D R / D ATA C O N T R OVLC C
0 1
0 M2
READ
L AT C H TB2

P0.X
1 PIN
INTERNAL D Q
CPU BUS P0.X M1
WRITE TO CLK Q
L AT C H

TB1
READ PIN

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WRITING “1” TO PORT 0
A D D R / D ATA C O N T R OVLC C
x 0
M2
READ
L AT C H TB2

P0.X
1 PIN
INTERNAL D Q Floating
CPU BUS P0.X Output
M1
0
WRITE TO CLK Q
L AT C H

TB1
READ PIN

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WRITING “0” TO PORT 0
A D D R / D ATA C O N T R OVLC C
x 0
0 M2
READ
L AT C H TB2

P0.X
0 PIN
INTERNAL D Q Floating
CPU BUS P0.X Output
M1
1
WRITE TO CLK Q
L AT C H

TB1
READ PIN

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WRITING “1” TO PORT 0
Vcc
A D D R / D ATA C O N T R OVLC C
x 0
M2
READ
L AT C H TB2

P0.X
1 P I N‘1’
INTERNAL D Q
CPU BUS P0.X M1
0
WRITE TO CLK Q
L AT C H

TB1
READ PIN

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WRITING “0” TO PORT 0
Vcc
A D D R / D ATA C O N T R OVLC C
x 0
0 M2
READ
L AT C H TB2

P0.X
0 PIN
INTERNAL D Q
CPU BUS P0.X
‘0’
M1
1
WRITE TO CLK Q
L AT C H

TB1
READ PIN

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INTERFACING PORT 0

Vcc
10 K

P0.0
P0.1

Port 0
P0.2
8051 P0.3
P0.4
P0.5
P0.6
P0.7

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Programming P0

• Using it as an output port: • Using it as an input port:

MOV A, #55H BACK: MOV P0, #0FFH

BACK: MOV P0, A MOV A, P0
ACALL DELAY MOV P1, A
CPL A SJMP BACK
SJMP BACK
– This will continuously read
– This will continuously output from port P0 and write the
01010101 followed by same value to port P1.
10101010 on P0 separated by – Port P0 is initialized as output
a certain delay. by default, so it needs to be
– Port P0 is initialized as output configured for input by
by default, so no need to writing 1’s to all of its bits.
configure it.

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PORT P2 AND ITS DUAL ROLE
P2 is very similar to P1 in its basic operation and in the
fact that it does not need external pull-up.

As it was shown for P0, P2 also serves as pins A8 – A15

(the upper 8 bits of he address bus) when accessing
external memory.
The upper 8 bits of the address will be kept on the P2 pins for
the duration of the memory cycle.
No need for external latching.

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INTERNAL STRUCTURE OF A PIN OF PORT 2

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ACCESSING EXTERNAL MEMORY
As it has been noted before, the 8051 does not have an address or
data bus. Instead, the pins of ports P0 and P2 are used for that
purpose.
The pins of port P0 double as AD0 – AD7 (multiplexed).
The pins of port P2 double as A8 – A15.

During a memory access (read from/write to external data

memory or instruction fetch from external program memory):
The pins of port P0 first carry the lower 8-bits of the address, then switch
operation to become the data bus.
The ALE signal is set to 1 during the period when the address is on the bus.
The pins of port P2 carry the upper 8-bits of the address through out the
memory access cycle.

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ACCESSING EXTERNAL MEMORY
What about the values that were on the ports
previously?
The values are stored in the latches in the SFR and are restored
after the memory access operation.
The one exception is P0 where the value stored in the register is
always over-written.
This is due to the use of the P0 pins for the bidirectional
data bus.

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ACCESSING EXTERNAL MEMORY
Access to external program memory always requires a 16-bit address.
Therefore, ports P0 and P2 are always used during external instruction fetch
operations.

Access to external data memory may use an 8-bit or 16-bit address

depending on the instruction.
MOVX A, @DPTR
– Uses a 16-bit address.
MOVX A, @R0
– Uses an 8-bit address.
However, using a value placed on P2 before the second MOVX instruction
allows us to provide a 16-bit address if necessary.

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PORT P3
P3 is similar to P1 and P2 in its basic operation and in the
fact that it does not need external pull-up.

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INTERNAL STRUCTURE OF A PIN OF PORT 3

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ALTERNATE FUNCTIONS OF THE P3 PINS
All P3 pins are multifunctional, they are not only I/O port
pins but they also serve special functions.

MSB LSB
P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0
RD WR T1 T0 INT1 INT0 TxD RxD

P3.7 Read Signal (Data) P3.3 External Interrupt

P3.6 Write Signal (Data) P3.2 External Interrupt
P3.5 Timer 1 external input P3.1 Serial Output
P3.4 Timer 0 external input P3.0 Serial Input

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DRIVING ABILITY
The pins of ports P1, P2, and P3 have a fanout of 4 LS TTL
inputs only.

The fanout of the pins of port P0 depends on the size of

the external resistor used for the pull-up.
You should not expect a fanout for P0 pins of more than 8
inputs.

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INTERNAL PULL-UP

The fixed part of the pull-up is a depletion mode transistor with the gate wired to
the source. This transistor will allow the pin to source about 0.25mA when shorted
to ground. In parallel with the fixed pull-up is an enhancement mode transistor,
which is activated during S1 whenever the port bit does a 0-to-1 transition. During
this interval, if the port pin is shorted to ground, this extra transistor will allow the
pin to source an additional 30mA.

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