Chng 1: Tng quan ASIC

Gii thiu v cng ngh ASIC Phn loi ASIC Cu trc FPGA
Cu trc FPGA tng qut Cng ngh lp trnh chip Cu trc FPGA ca mt s hng

Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng

Classifications of Integrated Circuits

Microprocessors Memory chips (SRAM, DRAM, Flash, ROM, PROM) Standard Components (74LS..) Application-Specific Integrated Circuits
Widely used in communication, network, and multimedia systems For a given application, ASIC solutions are normally more effective than the solutions based on running software on microprocessors Many chips in cellular phones, network routers, and game consoles are ASICs Most SoC (Systems-on-a-Chip) chips are ASICs
Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng 2

Gii thiu v cng ngh ASIC

ASIC (Application Specific Intergrated Circuit): Mch tch hp ng dng chuyn bit. ASIC c xy dng bng vic kt ni cc khi mch c sn c xy dng theo cc phng php mi. sn xut ASIC thun tin v d dng hn ASIC l mt mch tch hp c sn xut cho mt ng dng c trng v thng c kch thc tng i nh ng dng: rng khp trong cc thit b iu khin t ng iu khin cc chc nng ca cc phng tin truyn thng, xe c, cc h thng x l, dy chuyn cng nghip

Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng

S lc qu trnh pht trin ca mch tch hp IC

Mch tch hp vi mt rt cao (VLSI) Trong nhng nm 1980 cc k s bt u khai thc nhng u im thit k IC theo nhu cu ca mnh hoc thit k cc h thng, cc ng dng c bit hn so vi cc IC chun. n cui nhng nm 1980, cc ngn ng m t phn cng nh VHDL v Verilog ra i, cc b m phng tc cao cho php cc mu thit k c hiu lc nhanh chng. Cc cng c tng hp t ng phin dch hot ng ca m hnh HDL thnh mt m hnh cu trc logic.

Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng

Phn loi ASIC

Logic Standard Logic
Programmable Logic Devices

ASIC Gate Arrays Cell-Based ICs

(PLDs)

Full Custom ICs

SPLDs (PALs)

CPLDs

FPGAs

ASIC c ch hon ton ( Full- custom ASIC) ASIC da trn cc t bo chun ( Standard- Cell- Based ASIC) ASIC da trn mng cng logic (Gate- Array-Based ASIC) Cc vi mch lp trnh c ( PLD: Programmable Logic Device)
SPLD: Simple Programmable Logic Device CPLD (Complex Programmable LogicDevices) Mng cng logic c th lp trnh c theo trng/min (FPGA: Field Programmable Gate Array)

Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng

ASIC c ch hon ton ( Full- custom ASIC)

Mt phn hoc ton b cc logic cell v cc mch hoc nn (layout) c thit k ring bit cho tng ASIC. Khng s dng c th vin t bo c sn cho tt c hoc mt phn thit k. Gi thnh cao 8 tun ch to (khng k thi gian thit k)

Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng

ASIC da trn cc t bo chun ( Standard- Cell- Based ASIC)

Cn gi l CBIC (Cell-based ASIC ) s dng cc t bo logic thit k sn (cng AND, OR, MUX, FF) c gi l cc t bo chun. C th s dng kt hp t bo chun vi cc t bo ln c thit k sn (nh b VK, VXL) gi l siu t bo (megacell). Ngi thit k ch cn nh ngha v tr ca t bo chun v kt ni (interconnect) trong mt CBIC. Tt c cc lp mt n (mask layer) c ty bin v c thit k duy nht cho tng khch hng. u im: tit kim thi gian, tin bc v gim ri ro do s dng th vin t bo chun thit k sn v kim tra trc. Nhc im: Thi gian thit k hay chi ph mua th vin cell Thi gian ch to cc mask layer

Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng

ASIC da trn cc t bo chun ( Standard- Cell- Based ASIC)

Mt ASIC da trn t bo chun

CBIC cu to t 1 vng t bo chun (flexible block) v 4 khi c nh Khi linh hot cha cc hng ca cc t bo chun. Cc vung nh quang ra CBIC c ni n chn linh kin T bo chun c thit k gn ging vi cc vin gch xy tng.
8

Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng

ASIC da trn mng cng logic (Gate- Array-Based ASIC)

L ASIC c c sn bng mng cc cng hoc cc cell ging ht nhau nhng cha c kt ni vi nhau. Cc cell ny c t ti cc v tr xc nh trc. Ch vi lp kim loi trn cng, phn nh ngha kt ni gia cc cell l c nh ngha bi ngi thit k nh mt n ty bin mng cng mt n (MGA) Mng cng (GA) c to t cc basic cell, mi cell gm mt s trasistor v in tr ty thuc vo mi hng. Ngi thit k s dng mt th vin cell (cc gate, thanh ghi) v mt th vin macro (cc tnh nng phc tp hn) cng vi phn mm ca hng to ra mt n ty bin. Trong GA, do cc cell c t ti cc v tr c nh nn mt s cell s khng c dng n

Gate Array Cells.

Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng

Cc vi mch lp trnh c ( PLD: Programmable Logic Device)

PLD l cc IC chun. Tuy nhin PLD c th c cu hnh hay lp trnh to nn 1 b phn ty bin cho cc ng dng ring bit nn chng cng thuc h ASIC. c im chnh ca PLD
Logic cell v mask layer khng c ty bin Thit k nhanh, gi thnh r Mt khi n l ca kt ni c th lp trnh Mt ma trn ca siu t bo logic thng gm mng logic c th lp trnh c theo sau bi FF hoc Latch.
10

Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng

Cc vi mch lp trnh c ( PLD: Programmable Logic Device)

Programmable Logic Device (PLD, PLA, PAL, ...) AND-OR combinatorial logic, plus FF Cho php thc hin cc mch logic tc cao. Tuy nhin cu trc n gin ca n ch cho php hin thc cc mch logic nh. PLA (Program. Logic Array): Khi AND kh trnh, khi OR c nh PLA :Khi AND v OR u kh trnh. PLA c th l mask- programmable hay field- programmable. Complex PLD (CPLD) Gm vi khi PLD Ma trn cc kt ni kh trnh FPGA: mng logic c th lp trnh Chip c c sn vi cc khi logic v cc kt ni Cc khi logic v kt ni kh trnh (c th xa v lp trnh nhiu ln). Khng cn ch to Gi thnh thp, ph hp vi thit k c phc tp trung bnh (<1M gate)
Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng 11

CPLDs and FPGAs

Complex Programmable Logic Device (CPLD) Field-Programmable Gate Array (FPGA)

Architecture Density Performance Interconnect

PAL like More Combinational Low-to-medium 0.5-10K logic gates Predictable timing Up to 250 MHz today Crossbar Switch

Gate array-like More Registers + RAM Medium-to-high 1K to 3.2M system gates Application dependent Up to 600 MHz today Incremental
12

Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng

Cc vi mch lp trnh c ( PLD: Programmable Logic Device)

Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng

13

CPLD Architecture and Examples

Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng

14

PLD - Sum of Products

Programmable AND array followed by fixed fan-in OR gates
A B C

Programmable switch or fuse

f1 = A B C + A B C

f2 = A B + A B C

AND plane Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng 15

PLD - Macrocell
Can implement combinational or sequential logic
Select A B C Enable

f1
Flip-flop MUX D Q

Clock

AND plane

Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng

16

CPLD Structure
Integration of several PLD blocks with a programmable interconnect on a single chip
I/O Block I/O Block I/O Block I/O Block I/O Block I/O Block

PLD Block

PLD Block

Interconnection Matrix

I/O Block I/O Block

PLD Block

PLD Block

Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng

17

CPLD Example Altera MAX7000

EPM7000 Series Block Diagram

Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng 18

CPLD Example Altera MAX7000

EPM7000 Series Device Macrocell

Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng 19

Field-Programmable Gate Array (FPGA)

Khi nim c im/kh nng ng dng Cu trc tng qut Cng ngh lp trnh Cu trc FPGA ca mt s hng

Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng

20

Field-Programmable Gate Array (FPGA)

FPGA: mng cng logic c th lp trnh c theo trng/min FPGA l vi mch dng cu trc mng phn t logic m ngi dng c th lp trnh c. (Ch field y mun ch n kh nng ti lp trnh bn ngoi ca ngi s dng, khng ph thuc vo dy chuyn sn xut phc tp ca nh my bn dn). Vi mch FPGA c cu thnh t cc b phn:
Cc khi logic c bn lp trnh c (logic block) H thng mch lin kt lp trnh c Khi vo/ra (IO Pads) Phn t thit k sn khc nh DSP slice, RAM, ROM, nhn vi x l...

c im chnh ca FPGA

Logic cell v mask layer c sn (khng theo yu cu user) Cell v Interconnect kh trnh Li l 1 mng cc t bo logic c bn c th lp trnh, Mt ma trn cc kt ni c th lp trnh, bao quanh cc t bo logic c bn. T bo I/O c th lp trnh bao quanh li Thi gian thit k hon chnh kh nhanh (vi gi)

Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng

21

FPGA (cont.)

u im ca FPGAs

Kh nng ti lp trnh khi ang s dng Cng on thit k n gin (so vi ASIC) gim chi ph, th gian Kh nng cu hnh ng

ng dng FPGA

Nn tng l tng to mu Thit k v hon thin nhanh chng, gim thi gian a ra th trng Gii php hiu qu cho cc sn phm khng yu cu s lng ln Thc hin cc h thng phn cng yu cu kh nng ti lp trnh. Th hin cc h thng ti cu hnh ng.
Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng 22

FPGA - Cu trc chung

FPGA gm mt dy cc phn t ri rc c th c kt ni vi nhau theo mt kt ni chung, kt ni gia cc phn t ny c th lp trnh c
Logic block Interconnection switches

Cc khi trong FPGA:

Cc khi logic kh trnh s thc hin cc chc nng logic dy v t hp Cc kt ni kh trnh s kt ni cc u vo ra vi cc logic block. Cc khi I/O kh trnh: l cc khi logic c bit ti phn ngoi vi ca thit b cho cc kt ni vi bn ngoi. Mt s khi khc:
Phn phi Clock B nh nhng Cc khi c tnh nng c bit: DSP, Embbed Microprocessor/Microcontroller, High-speed serial transceiver
Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng

I/O

I/O I/O

I/O
23

FPGA Basic Logic Element

LUT thc hin mch logic t hp Thanh ghi thc hin mch logic Cc mch logic khc Thc hin chc nng s hc Cc mch logic m rng cho cc chc nng c hn 4 input.
Select

Out A B C D

LUT
Clock

Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng

24

Look-Up Tables (LUT)

Look-up table: bng tham chiu N-inputs c th thc hin bt k hm .t hp N u vo no LUT c lp trnh bng bng chn l
A B C D

LUT

LUT implementation
A B Z C D

Truth-table

Gate implementation
25

Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng

LUT Implementation
Example: 3-input X1 X2 LUT Configuration memory cells Based on multiplexers (pass transistors) LUT entries stored in configuration memory cells
X3 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 F

Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng

26

FPGA- kt ni kh trnh
Kt ni trong FPGA c kin trc nh tuyn, gm cc on dy ni v cc chuyn mch lp trnh c. Cc chuyn mch lp trnh c c th nhiu cu to khc nhau nh anti-fuse, EPROM v EEPROM transistor. LE LE LE LE Switch Matrix Switch Matrix LE LE

LE LE

LE LE

LE LE

Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng

27

FPGA- Cng ngh lp trnh chip

Cc phn t lp trnh : Cho php cc kt ni c th lp trnh c gia cc on dy ni. Chc nng: thc hin cc kt ni lp trnh c gia cc khi logic ca FPGA. Tnh cht:
C th c cu hnh 1 trong 2 trng thi ON hay OFF. Chim din tch ca chip cng nh cng tt C tr khng rt thp khi trng thi ON v tr khng rt cao khi trng thi OFF C in dung k sinh thp khi kt ni cc on dy C th tch hp mt s lng ln cc phn t lp trnh trong 1 chip C th lp trnh khng bay hi hoc c th lp trnh li c.
Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng 28

FPGA- Cng ngh lp trnh chip

Cng ngh lp trnh theo trng (field-programmable) .
Cng ngh lp trnh dng SRAM (RAM tnh): Mi chuyn mch l mt transistor truyn (pass)/ MUX c iu khin bng trng thi ca mt bit SRAM

Cng ngh lp trnh dng EPROM (UV light Erasable PROM) v EEPROM (Electrically Erasable PROM)
Mi chuyn mch l mt transistor cng treo (floating-gate), transistor ny c th ngt bng cch np in vo cng ca n. Bn thn FPGA lu tr chng trnh.

Cng ngh lp trnh dng cu ch nghch (anti-fuse)

Cu ch nghch bnh thng trng thi tr khng cao, nhng c th b nng chy thng trng thi in tr thp khi c lp trnh in th cao. Ch lp trnh 1 ln bng my lp trnh c bit

Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng

29

FPGA- Cng ngh lp trnh dng SRAM

Trng hp transistor truyn v cng truyn: nh SRAM iu khin cng truyn ON hay OFF. Khi OFF gia 2 dy ni vi pass-gate s c tr khng rt cao, khi ON n s to ra tr khng thp kt ni gia 2 dy ni Trng hp b dn knh: SRAM cell iu khin u vo no ca MUX s c kt ni vi u ra ca n.
Cc kt ni lp trnh c iu khin bng cc nh (cell) SRAM

nh Ram

nh RAM

ng ni

MUX ng ni nh RAM B ghp knh u vo

c im cng ngh lp trnh dng SRAM

ng ni

Chip c din tch ln v cn t nht 5 transistor cho mi RAM cell cng nh cc transistor cn thm cho cng truyn hay MUX. u im: cho php FPGA c ti cu hnh ngay trn mch rt nhanh v c th c ch to bng cng ngh CMOS chun.

Transistor truyn

Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng

30

FPGA- Cng ngh lp trnh dng EPROM

Thng dng lm chuyn mch lp trnh cho CPLD v SPLD EPROM hay EEPROM transistor c t gia 2 dy thc hin cc chc nng ni AND. Mt u vo ni n AND-Plane c th lm product wire chuyn thnh mc logic 0 thng qua EPROM. Vi cc u vo khc, EPROM c lp trnh lun ngt. . Phng php dng EEPROM (hng AMD) tng t EPROM, ngoi tr EEPROM transistor tn gp i din tch chip so vi EPROM v cn nhiu ngun in ti lp trnh.

Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng

31

FPGA- Cng ngh lp trnh dng cu ch nghch (anti-fuse)

Cu ch nghch bnh thng trng thi tr khng cao, nhng c th b nng chy thnh trng thi in tr thp khi c lp trnh in th cao. Cu trc anti-fuse PLICE ca Actel (Hnh ) hnh ch nht gm 3 lp : lp di cng cha silic mang nhiu in tch dng (n+), lp gia l lp in mi (oxit cch in) v lp trn cng l Poly-Silic. Din tch chip s dng dng cng ngh anti-fuse nh. Tuy nhin, cn c khng gian ln cho cc transistor in th cao cn gi dng v p cao lc lp trnh. Quy trnh ch to phi thay i so vi quy trnh ch to CMOS.

Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng

32

FPGA- Cng ngh lp trnh Tm tt

Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng

33

FPGA Vendors & Device Families

Xilinx
Virtex-II/Virtex-4: Featurepacked high-performance SRAM-based FPGA Spartan 3: low-cost feature reduced version CoolRunner: CPLDs Stratix/Stratix-II

Actel

Anti-fuse based FPGAs

Altera

Lattice

Flash-based FPGAs Flash-based FPGAs CPLDs (EEPROM) ViaLink-based FPGAs

34

Radiation tolerant

Cyclone/Cyclone-II

High-performance SRAM-based FPGAs Low-cost feature reduced version for cost-critical applications

QuickLogic

Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng

MAX3000/7000 CPLDs MAX-II: Flash-based FPGA

Xilinx FPGA Spartan IIE

Xilinx gm 1 mng 2 chiu cc khi lp trnh c (CLB: Configurreable Logic Block). iu khin lp trnh bng SRAM cell Khi logic c th cu hnh CLB I/O logic Block RAM Block: Gm nhiu khi RAM t chc thnh 2 ct 2 cnh ca Spartan. DLL (Delay Lock Loops vng kha tr): iu khin xung clock gim tr, to tr , ng b. gia cc tn hiu Clock. Mi DLL ni 2 mch xung nhp Clock ton cc.

Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng

35

Xilinx FPGA Spartan IIE Logic cell

Khi logic c th cu hnh CLB Mt CLB gm 4 logic-cell Mi Logic cell gm 2 LUT (Look-up Table) ging nhau Mi LUT gm 4 u vo, tn hiu iu khin v cc FF-D. Mi CLB c 2 b iu khin ng ra 3 trng thi BUFT
Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng 36

I/O logic Block: Mi IOB gm 3FF chung Clock v cc tn hiu CE (Clock Enable), iu khier c lp cho tng FF. Tn hiu vo qua 1 b m, tn hiu ra qua b m 3 trng thi theo cc chun b nh/ giao tip Bus

Xilinx FPGA Spartan IIE I/O Logic Block

Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng

37

Altera FPGA Cyclone

Gm mt mng ln cc dy Block lp trnh c gi l LAB (Logic Array Block) c kt ni vi nhau bi PIA (Programmable Interconnect Array). Cu trc h Cyclone gm cc khi c bn:
Cc dy logic cha cc bng LUT, B nh dng khi (dung lng M4K) Cc b ghp knh tch hp sn Cc khi vo ra (IOE) Cc vng kha pha (PLL): cung cp xung nhp, to s dch pha cho cc yu cu h tr u ra tc cao
Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng 38

Kin trc c bn

Altera FPGA Cyclone phn t logic LE

Cc dy logic cha rt nhiu phn t logic LE, 16 LE to nn 1 khi dy logic LAB (logic array Block)

Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng

39

Kch thc 1 LAB tng ng vi b nh dung lng 4K. Cc ng ni hng v ct gip cho vic y nhanh tc kt ni gia cc LE trong LAB v gia cc LAB vi nhau

Altera FPGA Cyclone LAB

Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng

40

Altera FPGA Cyclone khi b nh M4K

H Cyclone c b nh tch hp sn gm c 1 hay 2 dy khi b nh dung lng M4K. Mi khi M4K c th thc hin thanh ghi dch v nhiu kiu b nh khc nhau c hay khng c bit chn l, gm cc Ram, Rom, cc b m FIFO v cc thanh ghi dch.

Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng

41

Altera FPGA Cyclone khi vo ra IOE

Mi phn t vo ra IOE cha 1 b m vo ra 2 hng v 3 thanh ghi truyn dn tn hiu theo hai hng.

Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng

42

Actel FPGA Act-3

Gm cc hng nhng khi lp trnh c gi l LM (Logic Modul) vi cc knh kt ni ngang gia cc hng Actel FPGA dng cng ngh cu ch nghch anti-fuse PLICE Kin trc c bn ca Actel FPGA

Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng

43

Actel FPGA Act-3 Logic Modul

Khi logic c s LM ca h Act3, gm c 1 cng AND v OR kt ni ti mt khi mch to nn t cc b ghp knh. Khi mch ghp knh ny c thit k khi kt hp vi 2 cng logic (AND v OR) s c th cung cp mt lng ln cc hm. Khi logic c bn ca Actel l cc LM ny n gin v nh hn nhiu so vi nhng khi logic c bn ca cc FPGA cc hng khc. LM-khi logic c bn ca Act-3.

Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng

44

State of the Art in FPGAs

Xilinxs top of the line FPGA
65nm process technology Serial connectivity
550MHz RAM blocks 6-input LUTs

Enhanced DSP blocks (25x18-bit MAC) 1760 pin BGA with 1200 I/O EasyPath
Bi ging: Cng ngh ASIC v ng dng 1: Tng quan Cng ngh ASIC Chng 45

Ethernet MACs Rocket I/O serial 6.5 GBps PCI Express endpoint