Latches & Flip-Flops: Logic Circuits

Latches & Flip-Flops
Logic Circuits
Latches
 S-R latches
 The Gated S-R latches
 The Gated D latches
Flip Flops
• The Edge-Triggered S-R Flip-Flop
• The Edge-Triggered D Flip-Flop
• The Edge-Triggered J-K Flip-Flop
Shift Registers
S-R Latch
A latch is a type of bistable logic device or multivibrator.
Combinational logic circuits do not have a memory!

S-R (Set-Reset) Latch
if S=1, Q=1 (Q'=0);

if R=1, Q=0 (Q`=1)
if S=R=0, keep previous state (hold)
if S=R=1, undefined state
Active-low input S-R Latch
Figure 8--2 Negative-OR equivalent of the NAND gate S-R latch in Figure 8-1(b).
S’-R’ latch
operation
No change condition Invalid condition

Logic symbols
Example- Find Q output
Another example
The 74LS279 quad S’-R’ latch.
A gated S-R latch
•A gated latch requires an enable input, EN.
•The latch will not change until EN is HIGH.
•Inthis circuit, the invalid state occurs when both S and R

are simultaneously HIGH.
A gated S-R latch
A gated D latch
• Has only one input in addition to EN.
• The output Q follows the input when EN is HIGH.

A gated D latch
Flip-Flops
Flip-flops are synchronous bistable devices, also
known as bistable multivibrators.
In this case, the term synchronous means that the
output changes state only at a specified point (leading
or trailing edge) on the triggering input called the clock
(CLK), which is designated as a control input, C; that
is, changes in the output occur in synchronization with
the clock.
Edge-Triggered Flip-Flops
 The Edge-Triggered S-R Flip-Flop
 The Edge-Triggered D Flip-Flop
 The Edge-Triggered J-K Flip-Flop
Clock (Saat)
Clock Pulse (Saat Darbesi) Clock Frequency
Clock Period
IR2153, AD9833, AD9837, 555 timer, etc.
Edge-Triggered Flip-Flops
The Positive Edge-Triggered S-R Flip-Flop
The Positive Edge-Triggered S-R Flip-Flop
A method of Edge Triggering
Operation of Edge Triggering
S=1, R=0
Operation of Edge Triggering
S=0, R=1
The Edge-Triggered D Flip-Flop
The Edge-Triggered D Flip-Flop
The Edge-Triggered J-K Flip-Flop
•The functioning of the J-K flip-flop is identical to that of S-R flip-flop

in the SET, RESET and no-change conditions of operation
• Has no invalid states as does the S-R flip-flop.

Transitions illustrating the toggle operation
when J =1 and K = 1.
Example
Determine the Q output. Assume the flip-flop is initially in RESET state.
Example
Determine the Q output. Assume the flip-flop is initially in RESET state.
Asynchronous PRESET and CLEAR inputs
External inputs: PRE and CLR are the control inputs and prior for S, R, and CLK inputs.
Asynchronous PRESET and CLEAR inputs
Timing diagrams
74AHC74 Dual D flip-flops
74HC112 dual negative edge-
triggered J-K flip-flop
Example
Determine the 1Q output
for 74HC112.
Shift registers
Figure 10--1 The flip-flop as a storage element.
Thomas L. Floyd Copyright ©2003 by Pearson Education, Inc.

Digital Fundamentals, 8e Upper Saddle River, New Jersey 07458
All rights reserved.
Figure 10--2 Basic data movement in shift registers. (Four bits are used for illustration. The bits move in the direction of the arrows.)

Figure 10--3 Serial in/serial out shift register.

Figure 10--4 Four bits (1010) being entered serially into the register.

Figure 10--5 Four bits (1010) being serially shifted out of the register and replaced by all zeros.

Figure 10--6 Open file F10-06 to verify operation.

Figure 10--7 Logic symbol for an 8-bit serial in/serial out shift register.

Figure 10--8 A serial in/parallel out shift register.

Figure 10--9

Figure 10--10 The 74HC164 8-bit serial in/parallel out shift register.

Figure 10--10 (continued)

Figure 10--11 Sample timing diagram for a 74HC164 shift register.

Figure 10--12 A 4-bit parallel in/serial out shift register. Open file F10-12 to verify operation.

Figure 10--13

Figure 10--14 The 74HC165 8-bit parallel load shift register.


Figure 10--16 A parallel in/parallel out register.

Figure 10--17 The 74HC195 4-bit parallel access shift register.


Figure 10--19 Four-bit bidirectional shift register. Open file F10-19 to verify the operation.

Figure 10--20

Figure 10--21 74HC194 Bidirectional Universal Shift Register
Universal Shift Register


Figure 10--23 Four-bit and 5-bit Johnson counters.

Figure 10--24

Figure 10--25

Figure 10--26 A 10-bit ring counter. Open file F10-26 to verify operation.
A ring counter utilizes one flip-flop for each state in its sequence. It has the
advantage that decoding gates are not required. In the case of a 10-bit ring counter,
there is a unique output for each decimal digit.

Figure 10--27
Thomas L. Floyd
Digital Fundamentals, 8e
Initial state: 1010000000 Copyright ©2003 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Figure 10--28 The shift register as a time-delay device.
N_stage x time delay

Figure 10--29

Figure 10--30 Timing diagram showing time delays for the register in Figure 10-29.

Ring counter
Thomas L. Floyd
Digital Fundamentals, 8e Initially preset to 1000 Copyright ©2003 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
The end of the lesson.

Latches & Flip-Flops: Logic Circuits

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Latches & Flip-Flops: Logic Circuits

Uploaded by

Copyright:

Available Formats

Latches & Flip-Flops

Combinational logic circuits do not have a memory!

if S=1, Q=1 (Q'=0);

No change condition Invalid condition

•A gated latch requires an enable input, EN.

•The latch will not change until EN is HIGH.

•Inthis circuit, the invalid state occurs when both S and R

• Has only one input in addition to EN.

• The output Q follows the input when EN is HIGH.

•The functioning of the J-K flip-flop is identical to that of S-R flip-flop

• Has no invalid states as does the S-R flip-flop.

Thomas L. Floyd Copyright ©2003 by Pearson Education, Inc.

Thomas L. Floyd Copyright ©2003 by Pearson Education, Inc.

Thomas L. Floyd Copyright ©2003 by Pearson Education, Inc.

Thomas L. Floyd Copyright ©2003 by Pearson Education, Inc.

Thomas L. Floyd Copyright ©2003 by Pearson Education, Inc.

Thomas L. Floyd Copyright ©2003 by Pearson Education, Inc.

Thomas L. Floyd Copyright ©2003 by Pearson Education, Inc.

Thomas L. Floyd Copyright ©2003 by Pearson Education, Inc.

Thomas L. Floyd Copyright ©2003 by Pearson Education, Inc.

Thomas L. Floyd Copyright ©2003 by Pearson Education, Inc.

Thomas L. Floyd Copyright ©2003 by Pearson Education, Inc.

Thomas L. Floyd Copyright ©2003 by Pearson Education, Inc.

Thomas L. Floyd Copyright ©2003 by Pearson Education, Inc.

Thomas L. Floyd Copyright ©2003 by Pearson Education, Inc.

Thomas L. Floyd Copyright ©2003 by Pearson Education, Inc.

Thomas L. Floyd Copyright ©2003 by Pearson Education, Inc.

Thomas L. Floyd Copyright ©2003 by Pearson Education, Inc.

Thomas L. Floyd Copyright ©2003 by Pearson Education, Inc.

Thomas L. Floyd Copyright ©2003 by Pearson Education, Inc.

Thomas L. Floyd Copyright ©2003 by Pearson Education, Inc.

Thomas L. Floyd Copyright ©2003 by Pearson Education, Inc.

Universal Shift Register

Thomas L. Floyd Copyright ©2003 by Pearson Education, Inc.

Thomas L. Floyd Copyright ©2003 by Pearson Education, Inc.

Thomas L. Floyd Copyright ©2003 by Pearson Education, Inc.

Thomas L. Floyd Copyright ©2003 by Pearson Education, Inc.

Thomas L. Floyd Copyright ©2003 by Pearson Education, Inc.

Thomas L. Floyd Copyright ©2003 by Pearson Education, Inc.

N_stage x time delay

Thomas L. Floyd Copyright ©2003 by Pearson Education, Inc.

Thomas L. Floyd Copyright ©2003 by Pearson Education, Inc.

Thomas L. Floyd Copyright ©2003 by Pearson Education, Inc.

You might also like