MPMC - UNIT - 1 - All Slides

Unit– 1
MICROPROCESSORS AND
MICROCONTROLLERS
Vikas Kumar Tiwari

Assistant Professor – ECE
Vignan Institute of Technology & Sciences
Email: vikas.ystiwari@gmail.com
Linkedin: linkedin.com/in/vikas-tiwari-9a5b7843
Course Objectives
 To familiarize the architecture of microprocessors and
micro controllers
To provide the knowledge about interfacing techniques
of bus & memory.

To understand the concepts of ARM architecture
To study the basic concepts of Advanced ARM processors

Course Outcomes
Upon completing this course, the student will be able to
Understands the internal architecture, organization and assembly
language programming of 8086 processors.
Understands the internal architecture, organization and assembly
language programming of 8051/controllers
Understands the interfacing techniques to 8086 and 8051 based
systems.
Understands the internal architecture of ARM processors and basic
concepts of advanced ARM processors.

Unit Name Description
Syllabus
Unit- 1 8086 Architecture; Instruction About internal architecture, organization and
Set and Assembly Language assembly language programming of 8086
Programming of 8086 microprocessor
Unit- 2 Introduction to Microcontrollers; About the internal architecture, organization

8051 Real Time Control and assembly language programming of 8051
microcontroller
Unit- 3 I/O And Memory Interface; Serial About the interfacing techniques to 8086 and
Communication and Bus 8051 based systems
Interface
Unit- 4 ARM Architecture About the internal architecture of ARM

processors
Unit- 5 Advanced ARM Processors About the basic concepts of advanced ARM
processors
Syllabus

microcontroller
Interface

processors
processors
Syllabus

microcontroller
Interface

processors
processors
Syllabus

microcontroller
Interface

processors
processors
Syllabus

microcontroller
Interface

processors
processors
Syllabus

microcontroller
Interface

processors
processors
Computer Block Diagram
Microprocessor based System
(Computer)
Integrated Circuits
(Microprocessors and Microcontrollers)
Microprocessors Versus
Microcontroller
Microprocessors Versus
Microcontroller
Unit-I
8086
Microprocessor
Architecture
Instruction Set and
Assembly Language Programming of
8086
Microprocessor
Program controlled semiconductor device
(IC) which fetches (from memory),
decodes and executes instructions.
It is used as CPU (Central Processing Unit)

in computers.
16
Microprocessors Evolution
First Generation
Between 1971 – 1973
PMOS technology, non compatible
with TTL
4 bit processors  16 pins
8 and 16 bit processors  40 pins
Due to limitations of pins, signals
are multiplexed
Intel 4004 (4 bit processor)
17
Second Generation
Between 1973 – 1978
NMOS technology  Faster speed, Higher
density, Compatible with TTL
4 / 8/ 16 bit processors  40 pins
Ability to address large memory spaces and
I/O ports
Greater number of levels of subroutine nesting
Better interrupt handling capabilities
Intel 8085 (8 bit processor) 18

Third Generation
During 1978
HMOS technology  Faster speed, Higher
packing density
16 bit processors  40/ 48/ 64 pins
Easier to program
Dynamically relatable programs
Processor has multiply/ divide arithmetic
hardware
More powerful interrupt handling capabilities
Flexible I/O port addressing
Intel 8086 (16 bit processor)

19
Fourth Generation
During 1980s
Low power version of HMOS technology
(HCMOS)
32 bit processors
Physical memory space 224 bytes = 16 Mb
Virtual memory space 240 bytes = 1 Tb
Floating point hardware
Supports increased number of addressing
modes
Intel 80386
20
Fifth Generation
Pentium
21
Microprocessors
Evolution
First Generation
Between 1971 – 1973
PMOS technology, non compatible with TTL
4 bit processors  16 pins
Due to limitations of pins, signals are multiplexed
22
Microprocessors
Evolution
Second Generation
Between 1973 – 1978
First Generation Ability to address large memory spaces and I/O
Between 1971 – 1973 ports
PMOS technology, non compatible with TTL Greater number of levels of subroutine nesting
4 bit processors  16 pins Better interrupt handling capabilities
Due to limitations of pins, signals are multiplexed Intel 8085 (8 bit processor)
23
Microprocessors
Evolution
Third Generation
During 1978
HMOS technology  Faster speed, Higher packing
density
16 bit processors  40/ 48/ 64 pins
Easier to program
Processor has multiply/ divide arithmetic hardware
Second Generation
Intel 8086 (16 bit processor) Between 1973 – 1978
24
Microprocessors
Evolution
Fourth Generation
During 1980s
(HCMOS)
Third Generation 32 bit processors
During 1978 Physical memory space 224 bytes = 16 Mb
HMOS technology  Faster speed, Higher packing Virtual memory space 240 bytes = 1 Tb
density Floating point hardware
16 bit processors  40/ 48/ 64 pins Supports increased number of addressing
Easier to program modes
Processor has multiply/ divide arithmetic hardware Intel 80386
Second Generation
25
Microprocessors
Fifth Generation Pentium
During 1993
Evolution
Fourth Generation
During 1980s
(HCMOS)
Third Generation 32 bit processors
During 1978 Physical memory space 224 bytes = 16 Mb
HMOS technology  Faster speed, Higher packing Virtual memory space 240 bytes = 1 Tb
density Floating point hardware
16 bit processors  40/ 48/ 64 pins Supports increased number of addressing
Easier to program modes
Processor has multiply/ divide arithmetic hardware Intel 80386
Second Generation
26
After this…….
They Started calling it as…….
 Pentium series
 Xeon series
 Celeron series
 Itenium
 Core 2 Duo
 Core i series (i3, i5, i7, i9, …………)
8086 Microprocessor Overview
First 16- bit processor released by
INTEL in the year 1978
Originally HMOS, now manufactured

using HMOS III technique
Approximately 29,000 transistors, 40-

pin DIP, 5V supply
Does not have internal clock; external

asymmetric clock source with 33%
duty cycle
20-bit address to access memory 

can address up to 220 = 1 megabytes of
memory space.
28


pin DIP, 5V supply

duty cycle

memory space.
29


pin DIP, 5V supply

duty cycle

memory space.
30


pin DIP, 5V supply

duty cycle

memory space.
31


pin DIP, 5V supply

duty cycle

memory space.
32


pin DIP, 5V supply

duty cycle

memory space.
33


pin DIP, 5V supply

duty cycle

memory space.


pin DIP, 5V supply

duty cycle

memory space.
35
8086 Architecture
BIU and EU functions separately
8086 Microprocessor
Architecture
8086 Microprocessor
Architecture
Bus Interface Unit (BIU)
BIU fetches instructions, reads data

from memory and I/O ports, writes data
to memory and I/ O ports.
Execution Unit
(EU)
8086 Microprocessor
Architecture
Bus Interface Unit

(BIU)
Execution Unit (EU)
EU executes instructions that have already been

fetched by the BIU.
8086 Microprocessor
Architecture
8086 Microprocessor
Architecture BIU and EU functions separately

from memory and I/O ports, writes
data to memory and I/ O ports.
8086 Microprocessor
Execution Unit (EU)
EU executes instructions that have

already been fetched by the BIU.
8086 Microprocessor

from memory and I/O ports, writes
data to memory and I/ O ports.
Execution Unit (EU)
EU executes instructions that have

already been fetched by the BIU.
8086 Microprocessor
Architecture
BIU fetches instructions, reads data from memory and I/O ports, writes data
to memory and I/ O ports.
8086 Microprocessor
Architecture
Execution Unit (EU)
EU executes instructions that have already been fetched by

the BIU.
8086 Microprocessor
Architecture

8086 Microprocessor
Architecture
Execution Unit (EU) Bus Interface Unit (BIU)
EU executes instructions that have already been fetched by BIU fetches instructions, reads data from memory and I/O ports, writes data
the BIU. to memory and I/ O ports.

8086 Microprocessor Bus Interface Unit (BIU)
Architecture
Dedicated Adder to generate 20 bit

address
Segment Registers >> 48

Architecture
Four 16-bit segment registers
Code Segment (CS)

Data Segment (DS)
Stack Segment (SS)
Extra Segment (ES)
Segment Registers >> 49

Architecture
Segment
Registers
8086’s 1-megabyte The 8086 can directly Programs obtain access to code
memory is divided into address four segments (256 and data in the segments by
segments of up to 64K K bytes within the 1 M byte changing the segment register
bytes each. of memory) at a particular content to point to the desired
time. segments.
50
Architecture
Instruction queue
A group of First-In-First-Out (FIFO)

in which up to 6 bytes of instruction
code are pre fetched from the
memory ahead of time.
This is done in order to speed up the

execution by overlapping instruction
fetch with execution.
This mechanism is known as

pipelining.
51
8086 Microprocessor
Architecture Execution Unit (EU)
EU decodes and executes

instructions.
A decoder in the EU control system

translates instructions.
Four general purpose registers(AX,

BX, CX, DX);
Pointer registers (Stack Pointer, Base

Pointer);
and
Index registers (Source Index,

Destination Index) each of 16-bits
Some of the 16 bit registers can be used as two 8 bit

registers as :
AX can be used as AH and AL

BX can be used as BH and BL
CX can be used as CH and CL 52
DX can be used as DH and DL
8086 Microprocessor

instructions.

16-bit ALU for performing

arithmetic and logic operation

registers as :

8086 Microprocessor

instructions.

It directs and synchronizes the

internal operations
registers as :

Register Organization of 8086
 The 8086 has a powerful set of registers. It includes
• General purpose registers,
• Segment registers,
• Pointers, Index registers,
• Flag register.
 The registers organization of 8086 is shown below. All registers are 16-bit
registers.
Generation of 20-bit Address
 The logical addresses that occur in the 8086
program are always 16 bits in length.
 This is because all registers are 16 bits.
 However, the physical addresses that are used

to access memory are 20 bits in length.
 The generation of the physical address involves

combining a 16-bit offset value that is located in
either an index register or pointer register and a
16-bit Segment base value that is located in
one of the segment register.
8086 registers categorized into 4 groups
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF DF IF TF SF ZF AF PF CF
Sl.No Type Register width Name of register
16 bit AX, BX, CX, DX

General purpose register
1 8 bit AL, AH, BL, BH, CL, CH, DL, DH
2 Pointer register 16 bit SP, BP
3 Index register 16 bit SI, DI
4 Instruction Pointer 16 bit IP
5 Segment register 16 bit CS, DS, SS, ES
6 Flag (PSW) 16 bit Flag register

57
Architecture
BIU
Code Segment Register
Registers
Segment 16-bit
Registers
CS contains the base or start of the current code segment; IP
contains the distance or offset from this address to the next
instruction byte to be fetched.
BIU computes the 20-bit physical address by logically shifting the

contents of CS 4-bits to the left and then adding the 16-bit contents
of IP.
That is, all instructions of a program are relative to the contents of

the CS register multiplied by 16 and then offset is added provided by
the IP.
58
Architecture
BIU Data Segment Register

Registers
Segment
Registers 16-bit
Points to the current data segment; operands for most instructions

are fetched from this segment.
The 16-bit contents of the Source Index (SI) or Destination Index

(DI) or a 16-bit displacement are used as offset for computing the
20-bit physical address.
59
Architecture
BIU Stack Segment Register

Registers
Segment 16-bit
Registers
Points to the current stack.
The 20-bit physical stack address is calculated from the Stack

Segment (SS) and the Stack Pointer (SP) for stack instructions
such as PUSH and POP.
In based addressing mode, the 20-bit physical stack address is

calculated from the Stack segment (SS) and the Base Pointer (BP).
60
Architecture
BIU Extra Segment Register

Registers
Segment
Registers 16-bit
Points to the extra segment in which data (in excess of 64K pointed
to by the DS) is stored.
String instructions use the ES and DI to determine the 20-bit

physical address for the destination.
61
Architecture
Instruction Pointer
BIU
Registers
Instruction 16-bit
Pointer
Always points to the next instruction to be executed within the
currently executing code segment.
So, this register contains the 16-bit offset address pointing to

the next instruction code within the 64Kb of the code segment
area.
Its content is automatically incremented as the execution of the

next instruction takes place.
62
8086 Microprocessor Execution Unit (EU)
Architecture
EU Accumulator Register (AX)

General
purpose
Registers Consists of two 8-bit registers AL and AH, which can be
combined together and used as a 16-bit register AX.
AL in this case contains the low order byte of the word, and AH
contains the high-order byte.
The I/O instructions use the AX or AL for inputting / outputting

16 or 8 bit data to or from an I/O port.
Multiplication and Division instructions also use the AX or AL.
63
Architecture
EU Base Register (BX)

Registers
Consists of two 8-bit registers BL and BH, which can be combined

together and used as a 16-bit register BX.
BL in this case contains the low-order byte of the word, and BH

contains the high-order byte.
This is the only general purpose register whose contents can be used
for addressing the 8086 memory.
All memory references utilizing this register content for addressing

use DS as the default segment register.
64
Architecture
EU Counter Register (CX)

Registers
Consists of two 8-bit registers CL and CH, which can be combined
together and used as a 16-bit register CX.
When combined, CL register contains the low order byte of the word,
and CH contains the high-order byte.
Instructions such as SHIFT, ROTATE and LOOP use the contents of

CX as a counter.
Example:
The instruction LOOP START

automatically decrements CX by 1
without affecting flags and will check if
[CX] = 0.
If it is zero, 8086 executes the next

instruction; otherwise the 8086
branches to the label START.
65
Architecture
EU
Registers
66
Architecture
Stack Pointer (SP) and Base Pointer (BP)

EU
Pointing SP and BP are used to access data in the stack segment.
Registers
SP is used as an offset from the current SS during execution of
instructions that involve the stack segment in the external
memory.
SP contents are automatically updated (incremented/

decremented) due to execution of a POP or PUSH instruction.
BP contains an offset address in the current SS, which is used by

instructions utilizing the based addressing mode.
67
Architecture
EU Source Index (SI) and Destination Index (DI)

Index
Registers Used in indexed addressing.
Instructions that process data strings use the SI and DI

registers together with DS and ES respectively in order to
distinguish between the source and destination addresses.
68
Registers and Special Functions
Register Name of the Register Special Function
Stores the 16-bit results of arithmetic and logic operations

AX 16-bit Accumulator

AL 8-bit Accumulator
Used to hold base value in base addressing mode to access memory data
BX Base register
Used to hold the count value in SHIFT, ROTATE and LOOP instructions
CX Count Register
Used to hold data for multiplication and division operations

DX Data Register
Used to hold the offset address of top stack memory

SP Stack Pointer
Used to hold the base value in base addressing using SS register to access data from
BP Base Pointer stack memory
Used to hold index value of source operand (data) for string instructions
SI Source Index
Used to hold the index value of destination operand (data) for string operations
DI Data Index
69
8086
Flag Register
“One Day Indian Team Selected Zaheer And Played Cricket”
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X X X X OF DF IF TF SF ZF X AF X PF X CF
70
Architecture
Flag Register
“One Day Indian Team Selected Zaheer And Played Cricket”

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
“Overflow Direction Interrupt Trap Sign Zero Auxiliary Parity Carry”
71
8- bit Data
<-- Byte -->
7 6 5 4 3 2 1 0
Higher Nibble Lower Nibble
72
Data in 8086
16- bit Data
<- Higher Byte -
<- Lower Byte ->
>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Highest Nibble Lowest Nibble
73
Architecture
Flag Register
Carry Flag
This flag is set, when there is a carry

out of MSB in case of addition or a
borrow in case of subtraction.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
74
Architecture
Flag Register
Parity Flag
This flag is set to 1, if the lower

byte of the result contains even
number of 1’s ; for odd number
of 1’s resets to zero.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
75
Architecture
Flag Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Auxiliary Carry Flag
This is set, if there is a carry from the

lowest nibble, i.e, bit three during
addition, or borrow for the lowest
nibble, i.e, bit three, during
subtraction.
76
Architecture
Flag Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Zero Flag
This flag is set, if the result of the

computation or comparison performed
by an instruction is zero
77
Architecture
Flag Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Sign Flag
This flag is set, when the result of any

computation is negative
78
Architecture
Flag Register
Tarp Flag
If this flag is set, the processor enters
the single step execution mode by
generating internal interrupts after the
execution of each instruction
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
79
Architecture
Flag Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Interrupt Flag
Causes the 8086 to recognize external

maskble interrupts; clearing IF disables
these interrupts.
80
Architecture
Flag Register Direction Flag

This is used by string manipulation instructions. If
this flag bit is ‘0’, the string is processed beginning
from the lowest address to the highest address, i.e.,
auto incrementing mode. Otherwise, the string is
processed from the highest address towards the
lowest address, i.e., auto decrementing mode.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
81
Architecture
Flag Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Over flow Flag

This flag is set, if an overflow occurs, i.e, if the
result of a signed operation is large enough to
accommodate in a destination register. The
result is of more than 7-bits in size in case of
8-bit signed operation and more than 15-bits
in size in case of 16-bit sign operations, then
the overflow will be set.
82
Architecture
Auxiliary Carry Flag Carry Flag

Flag Register
This is set, if there is a carry from the lowest nibble, i.e, This flag is set, when there is a carry out of
bit three during addition, or borrow for the lowest nibble, MSB in case of addition or a borrow in case of
i.e, bit three, during subtraction. subtraction.
Sign Flag Zero Flag Parity Flag
This flag is set, when the result of any This flag is set, if the result of the computation This flag is set to 1, if the lower byte of the result
computation is negative or comparison performed by an instruction is contains even number of 1’s ; for odd number of
zero 1’s set to zero.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Over flow Flag Tarp Flag

This flag is set, if an overflow occurs, i.e, if the result of a signed operation is large enough If this flag is set, the processor enters the single
to accommodate in a destination register. The result is of more than 7-bits in size in case step execution mode by generating internal
of 8-bit signed operation and more than 15-bits in size in case of 16-bit sign operations, interrupts after the execution of each instruction
then the overflow will be set.
Direction Flag Interrupt Flag

This is used by string manipulation instructions. If this flag bit is ‘0’, the string is
processed beginning from the lowest address to the highest address, i.e., auto Causes the 8086 to recognize external maskble
incrementing mode. Otherwise, the string is processed from the highest address interrupts; clearing IF disables these interrupts.
towards the lowest address, i.e., auto decrementing mode. 83
Registers and Special Functions
Register Name of the Register Special Function

AX 16-bit Accumulator

AL 8-bit Accumulator
Used to hold base value in base addressing mode to access memory data
BX Base register
Used to hold the count value in SHIFT, ROTATE and LOOP instructions
CX Count Register
Used to hold data for multiplication and division operations

DX Data Register
Used to hold the offset address of top stack memory

SP Stack Pointer
Used to hold the base value in base addressing using SS register to access data from
BP Base Pointer stack memory
Used to hold index value of source operand (data) for string instructions
SI Source Index
Used to hold the index value of destination operand (data) for string operations
DI Data Index
84
Memory Segmentation
Two types of memory addressing are

commonly used. There are
Linear addressing
Segmented addressing
Memory Segmentation
Linear Addressing
In linear addressing: the entire memory
space is available to the process in one
linear array.
“Was used in earlier Processors like 8080

and 8085”
Memory Segmentation
Segmented Addressing
In segmented addressing: the available
memory space is divided into “chunks‟
called segments.
Memory Segmentation
Linear Addresses
Segmented Addresses
Memory Segmentation
Segmentation is the process in which
the main memory of the computer is
logically divided into different segments
and each segment has its own base
address. It is basically used to enhance
the speed of execution of the computer
system, so that the processor is able to
fetch and execute the data from the
memory easily and fast.
Memory Segmentation
 Such memory is known segmented
memory. In 8086 system the available
memory space is 1Mbytes.
 This memory is divided into number of

logical segments. Each segment is
64Kbytes in size and addresses by one of
the segment registers.
The 16-bit contents of the segment register

give the starting/base address of a
particular segment.
Memory Segmentation
Types Of Segmentation –
Overlapping Segment – A segment starts
at a particular address and its maximum size can go
up to 64kilobytes. But if another segment starts along
with this 64kilobytes location of the first segment, then
the two are said to be Overlapping Segment.
Non-Overlapped Segment – A segment

starts at a particular address and its maximum size
can go up to 64kilobytes. But if another segment starts
before this 64kilobytes location of the first segment,
then the two segments are said to be Non-Overlapped
Segment.
Memory Segmentation
Segment
Registers
The 8086 can directly Programs obtain access to code

8086’s 1-megabyte and data in the segments by
address four segments (256
memory is divided into changing the segment register
K bytes within the 1 M byte
segments of up to 64K content to point to the desired
of memory) at a particular
bytes each. segments.
time. 92
Memory Segmentation
Advantages of the Segmentation:
The main advantages of segmentation are as

follows:
It provides a powerful memory management

mechanism.
Data related or stack related operations can be

performed in different segments.
Code related operation can be done in separate

code segments.
Memory Segmentation
Advantages of the Segmentation:
(Contd…)
It allows to processes to easily share data.
It allows to extend the address ability of the

processor, i.e. segmentation allows the use of
16 bit registers to give an addressing capability
of 1 Megabytes. Without segmentation, it would
require 20 bit registers.
It is possible to enhance the memory size of

code data or stack segments beyond 64 KB by
Generation of 20-bit Address
 The logical addresses that occur in the 8086
program are always 16 bits in length.
 This is because all registers are 16 bits.
 However, the physical addresses that are used

to access memory are 20 bits in length.
 The generation of the physical address involves

combining a 16-bit offset values that is located
in either an index register or pointer register and
a 16-bit Segment base value that is located in
one of the segment register.
The table below shows the offset registers
with their related segment registers
Segment Segment Offset Function

Register Register
Address of the next
Code Segment CS IP instruction
Data Segment DS SI, DI, BX Address of the Data

Address of the Data
Stack Segment SS SP,BP in the Stack Memory
Address of the Data

Extra Segment ES (Address of destination
DI, SI, BX data for string
Operations)
Physical Address Generation
Physical Address Generation
The table below shows the offset registers
with their related segment registers
Segment Segment Offset Function

Register Register
Address of the next
Code Segment CS IP instruction
Data Segment DS SI, DI, BX Address of the Data

Address of the Data
Stack Segment SS SP,BP in the Stack Memory
Address of the Data

Extra Segment ES (Address of destination
DI, SI, BX data for string
Operations)
Example:
If CS=2500 h & IP=95F3 h, what is the physical address?
Segment
Address
Example:
Segment
Address
Shifted by 1
digit in Hex
Example:
Offset
Address
Example:
Physical
Address
Example:
Segment
Address Segment
Address
Shifted by 1
digit in Hex
Offset
Address
Physical
Address
Example: The following operation illustrates the
generation of 20-bit physical address from CS and IP
registers.
Let: CS = 3 4 8 A H , IP= 4 2 1 4 H
Therefore,
Physical Address = Segment Register content
(Shifted by 1 digit in Hexadecimal) + Offset Register Content
Example:
If CS=24F6h & IP=634Ah, show the;
1- The logical address
2- The offset address Segment
3- The physical address Address
4- The lower range of the segment
5- The upper range of the segment Segment
Address
Shifted by
1 digit in
Hex
Offset
Address
Solution:
1- The logical address is the CS: IP content which is:
24F6:634A Physical
2- The offset address is the content of the IP register Address
which is: 634A
3- The physical address: 2B2AA
4- The lower range of the
segment:
5- The upper range of the

segment:
Top of the
segment
Bottom of
the
segment
The Programming Model of 8086
The programming model of the 8086 through
the Pentium II is considered to be program
visible because its registers are used during
application programming and are specified by the
instructions. Other registers, are considered to
be program invisible because they are not
addressable directly during applications
programming, but may be used indirectly during
system programming. Only the 80286 and above
contain the program-invisible registers used to
control and operate the protected memory
system.
The Programming Model of 8086
Computer Languages
High Level Low Level
Assembly Language
 English Alphabets
‘Mnemonics’
 Assembler Mnemonics 
Machine Language
Machine Language
 Binary bits
8086 Microprocessor
Introduction to Assembly Language Program
Program
A set of instructions
written to solve a
problem.
113
8086 Microprocessor
Instruction
Directions which a
microprocessor follows
to execute a task or part
of a task.
114
8086 Microprocessor
Assembler Directive
Hints/Directions given to
assembler, which helps it
to correctly understand the
program for generating
OpCodes
115
8086 Microprocessor
Comments
Explanation or
Annotations, are
added with the
purpose of making
the source code
easier for humans to
understand, and are
generally ignored by
compilers and
interpreters.
116
8086 Pin Diagram
01/23/17
AD0-AD15 (Bidirectional)
Address/Data bus
Low order address bus; these are multiplexed with

data.
When AD lines are used to transmit memory

address the symbol A is used instead of AD, for
example A0-A15.
When data are transmitted over AD lines the symbol

D is used in place of AD, for example D0-D7, D8-D15 or
D0-D15.
A16/S3, A17/S4, A18/S5, A19/S6
High order address bus. These are multiplexed with

status signals
Physical Memory
Organization in 8086 System
8086 System has 1 Mega byte
Memory Addressing capability,
which is Physically Organized into
two separate banks as Odd bank
and Even bank each having 512 K
Bytes
Physical Memory Organization in 8086 System
8086 System
BHE = 0 A0 = 0
Odd Even
Address Address
Bank Bank
8086 1 2
Processor D0 – D7 D0 – D7
Higher Byte Lower Byte
D8 - D15
D0 – D7
Physical Memory Organization in 8086
System
Read/Write Operation between Processor
and Memory
Pins and Signals
Of 8086
As observed earlier while discussing features of
Microprocessor 8086, that 8086 can operate into two
modes:
Minimum Mode
Maximum Mode
The pins/signals of 8086 are divided into three

categories:
 Minimum Mode Signals
 Maximum Mode Signals and
 Common Mode Signals

8086 Microprocessor
Pins and Signals Common signals
AD0-AD15 (Bidirectional)
Address/Data bus
Low order address bus; these
are multiplexed with data.
When AD lines are used to

transmit memory address the
symbol A is used instead of AD,
for example A0-A15.
When data are transmitted over

AD lines the symbol D is used in
place of AD, for example D0-D7,
D8-D15 or D0-D15.
125
8086 Microprocessor
Pins and Signals
Common signals
A16/S3, A17/S4, A18/S5, A19/S6
High order address bus. These are

multiplexed with status signals
126
8086 Microprocessor
(Active Low)/S7
(Output)
Bus High
Enable/Status
It is used to enable data

onto the most significant
half of data bus, D8-D15. 8-bit
device connected to upper
half of the data bus use BHE
(Active Low) signal. It is
multiplexed with status
signal S7.
127
8086 Microprocessor
MINIMUM / MAXIMUM
This pin signal indicates

what mode the processor is
to operate in.
128
8086 Microprocessor
Pins and Signals Min/ Max Pin
The 8086 microprocessor can work in two

modes of operations : Minimum mode and
Maximum mode
Minimum
Mode
Signals
Maximum
Mode
Signals 129
8086 Microprocessor
Minimum or Maximum mode operations are

decided by the pin MN/ MX(Active low).
When this pin is high 8086 operates in

Minimum mode otherwise it operates in
Maximum mode.
130
8086 Microprocessor
Minimum or Maximum mode operations are

decided by the pin MN/ MX(Active low).
When this pin is high 8086 operates in

Minimum mode otherwise it operates in
Maximum mode.
131
8086 Microprocessor
Pins and Signals Minimum Mode Pins

Maximum mode.
In the Minimum mode of operation the

microprocessor do not associate with any
co-processors and can not be used for
multiprocessor systems.
Minimum
Mode
Signals
132
8086 Microprocessor
Pins and Signals Maximum Mode Pins

Maximum mode.
In In the Maximum mode the 8086 can

work in multi-processor or co-processor
configuration.
Maximum
Mode
Signals
133
8086 Microprocessor
(Active Low)
READ
The signal is used for read
operation.
It is an output signal.
It is active when low
134
8086 Microprocessor
(Active Low)
This input is examined by ‘WAIT’ instruction.
8086 will enter a Idle State after execution of

the ‘WAIT’ instruction and will resume execution
only when the TEST is made low.
This is used to synchronize an external activity

to the processor internal operation.
135
8086 Microprocessor
READY
This is the acknowledgement from the slow

device or memory that they have completed
the data transfer.
The signal made available by the devices is

synchronized by the 8284A clock generator to
provide ready input to the 8086.
The signal is active high.
136
8086 Microprocessor
RESET (Input)
Causes the processor to immediately

terminate its present activity.
The signal must be active HIGH for at

least four clock cycles.
137
8086 Microprocessor
CLK
The clock input provides the basic timing

for processor operation and bus control
activity. Its an asymmetric square wave
with 33% duty cycle.
138
8086 Microprocessor
INTR Interrupt Request
This is a Level triggered input. This is sampled

during the last clock cycles of each instruction
to determine the availability of the request. If
any interrupt request is pending, the
processor enters the interrupt acknowledge
cycle.
This signal is active high and internally

synchronized.
139
8086 Microprocessor
NMI
(Non- Maskable Interrupt)
This is an Edge-triggered input which causes a

Type-2 interrupt. NMI is not maskable
internally by software.
A transition from low to high initiates the

interrupt at the end of current instruction and
internally synchronized.
140
8086 Microprocessor
Pins and Signals Minimum Mode Signals
Minimum
Mode
Signals
141
8086 Microprocessor
142
8086 Microprocessor
143
8086 Microprocessor
144
8086 Microprocessor
145
8086 Microprocessor
ALE (Address Latch Enable) Used to demultiplex the

address and data lines using external latches
146
8086 Microprocessor
147
8086 Microprocessor
HOLD Input signal to the processor from the bus master (Bus Controller) as
a request to grant the control of the bus.
Usually used by the DMA controller to get the control of the bus. 148
8086 Microprocessor
HLDA (Hold Acknowledge) Acknowledge signal by the processor to the bus

master(Bus Controller) requesting the control of the bus through
HOLD.
The acknowledge is asserted high, when the processor accepts 149

8086 Microprocessor
Minimum
Mode
Signals
150
8086 Microprocessor
151
8086 Microprocessor
152
8086 Microprocessor
153
8086 Microprocessor
154
8086 Microprocessor
ALE (Address Latch Enable) Used to demultiplex the

address and data lines using external latches
155
8086 Microprocessor
156
8086 Microprocessor
HOLD Input signal to the processor from the bus master (Bus Controller) as
a request to grant the control of the bus.
Usually used by the DMA controller to get the control of the bus. 157
8086 Microprocessor
HLDA (Hold Acknowledge) Acknowledge signal by the processor to the bus

master(Bus Controller) requesting the control of the bus through
HOLD.
The acknowledge is asserted high, when the processor accepts 158

8086 Minimum Mode System
8086 Minimum Mode Read Cycle
8086 Minimum Mode Write Cycle
Maximum
Mode
Signals
162
8086 Microprocessor
Pins and Signals Maximum Mode Signals
QS1 QS0
163
8086 Microprocessor
164
8086 Microprocessor
165
8086 Microprocessor
Active
166
8086 Microprocessor
LOCK
167
8086 Microprocessor
168
8086 Maximum Mode System
8086 Maximum Mode Read Cycle
8086 Maximum Mode Write Cycle
INTERRUPT
An Interrupt is a condition that causes the
microprocessor to temporarily work on a
different task and then return to its previous
task. Interrupt is an event or signal that
request to attention of CPU
Types of Interrupts in Microprocessor
8086 System
Interrupts
Software Interrupt
Hardware Interrupt
(INT n)
Maskable Interrupt Non- Maskable 256 Types of

(INTR) Interrupt (NMI) Software Interrupt
8086 System
Interrupts
Software Interrupt
Hardware Interrupt
(INT n)
The Programmer
can Choose to
mask specific
Maskable Interrupt Non- Maskable
interrupts and re 256 Types of
enable them later
8086 System
Interrupts
Software
The Interrupt
Programmer cannot
Hardware Interrupt Control when
(INT n) a Non-
Maskable Interrupt is
served.
The processor has to
execute the NMI Service
Routine

8086 System
Interrupts
Software Interrupt
Hardware Interrupt (INT n)
256 Types of 0 < n < 255
Software Interrupts
INT 00H
to
INT FFH

Types of Software Interrupts
INT 00 (divide error)
INT 01 (single step)
INT 02 (non-maskable)
INT 03 (breakpoint)
INT 04 (signed number overflow)
INT 05 to INT 255 (reserved)
Some Reserved Interrupts:

DOS INT 21H , BIOS INT 10H
Dedicated Interrupts Type 0 to Type 4
Type – 0 :- Divide by Zero Error Interrupt
(Quotient is large, cant be fit in AL/AX or divide by zero)
Type –1 :- Single step or Trap Interrupt
(Used for executing the program in single step mode by setting trap
flag)
Type – 2 :- Non-Maskable Interrupt
(This interrupt is used for executing ISR of NMI pin (positive edge
signal), NMI can’t be masked by S/W)
Type – 3 :- Break Point Interrupt
(Used for providing break points in the program; The breakpoint
feature executes all the instructions up to the inserted breakpoint
and then stops execution)
Type – 4 :- Over flow Interrupt
(Used to handle any overflow error after signed arithmetic)
Processing of Interrupts in 8086
System
8086 Interrupt Processing Steps
If an interrupt has been requested, the 8086 Microprocessor
processes it by performing the following series of steps:
1. Pushes the content of the flag register onto the stack to preserve
the status of IF and TF flags, by decrementing the stack pointer
(SP) by 2
2. Disables the INTR interrupt by clearing IF in the flag register
3. Resets TF in the flag register, to disable the single step or trap
interrupt
4. Pushes the content of the code segment (CS) register onto the
stack by decrementing SP by 2
5. Pushes the content of the instruction pointer (IP) onto the stack
by decrementing SP by 2
6. Performs an indirect far jump to the start of the interrupt service
routine (ISR) corresponding to the received interrupt.
ISR Address Calculation from the given Interrupt
Number
Instruction Mnemonics Associated with
Interrupts
What happens on RESET?
It causes the processor to immediately terminate its
present activity. The 8284 clock generator provides this
signal.
This signal must be active high for at least 4 clock cycles.
It clears all the flag register, the Instruction Queue, the
DS, SS, ES and IP registers and sets the bits of CS
register.
Hence the reset vector address of 8086 is FFFF0H (as
CS = FFFFH and IP = 0000H).
Instruction Formats in
8086 Assembly
Language
Programming
Instruction Format
Instruction Format
A machine language instruction format has more than one
number of field
1st field is called operation code field or op-code 
indicates the type of operation to be performed by the
CPU.
2nd field is called operand field  indicates data field on
which the operation by instruction op-code.
Length of an instruction may vary from 1 byte to 6 byte
It has 6 general format of instruction in 8086 instruction
set.
Operation code Operand field i.e
field or op-code data field
op-code byte:
- This byte is always present in each instruction .
This indicates the operation to be carried out by 8086
Format of op-code byte:-

Operation code
field or op-code
Op-code D W
Most of the opcodes in 8086 has a special 1-bit
indicates.
They are :
W-bit : Some instructions of 8086 can operate on byte or a word.
The W-bit in the opcode of such instruction specify whether
instruction is a byte instruction (W = 0) or a word instruction (W =
1).
D-bit : The D-bit in the opcode of the instruction indicates that
the register (REG) specified within the instruction is a source
register (D = 0) or destination register (D =1).
Instruction Format
The opcode/operand mode byte(s) may
be followed by :
No additional byte
One or two byte immediate operand
Two byte EA (For direct addressing only).
One or two byte displacement
One or two byte displacement followed by a one or two
byte immediate operand
Two byte displacement and a two byte segment address
(for direct intersegment addressing only).
Instruction Format
One Byte Instructions
This format is only 1 byte long and
may have implicit data or register
operands.
The least 3 bits of op-code are used
to specify the register operand.
Otherwise all the 8 bit form an op-
code and the operand are implied.
REG field
Register to Register
 This format is 2 byte long
 1st byte of code consist of operation code
of instruction and width of the operand
specified by w bit.
 2nd byte of code consist of register & R/M
field.
 REG indicates the name of the register i.e
source or destination.
 R/M indicates source or destination operand
is located in register
R/M field
Register to/from Memory with no displacement
 This format is also 2 byte long
 1st byte of code same as that of
register to register format
 2nd byte of code consist of MOD ,
REG,R/M field.
 MOD indicates the displacement is
present or not .if present then it is
8bit or 16 bit.
Mod field
Mod Displacement
0 0 No displacement
0 1 Low order displacement with sign

extended to 16 bit
1 0 Low order and high order

displacement
1 1 ‘R/M’ field is treated as a ‘REG’ field
Register to/from Memory with displacement
 This type of instruction format contain
one or two additional bytes for
displacement along with 2 byte format
of register to/from memory without
displacement
Immediate operand to Register
 In this format first byte as well as the
3 bits from the second byte which are
used for REG field in case of register –
to-register are used for op-code
Immediate operand to memory with 16 bit displacement
 This type of instruction format requires 5 or
6 byte for coding
 The first two byte contain the information of
OPCODE ,MOD ,R/M field
Converting Assembly Language Instruction to
Machine Code
Converting Assembly Language Instruction to
Machine Code
ADDRESSING MODES
ADDRESSING
MODES
 Every instruction of a program has to operate
on a data.
“The different ways in which a source

operand is denoted in an instruction
are known as Addressing Modes”
Addressing Modes
1.Register Addressing Group I : Addressing

modes for register and
2.Immediate Addressing immediate data
208
Addressing Modes
3. Direct Addressing
4. Register Indirect Addressing
5. Based Addressing Group II : Addressing

modes for memory data
6. Indexed Addressing
7. Based Indexed Addressing
8. Relative Based Indexed Addressing

209
Addressing Modes
9. String Addressing Group III : String

Addressing mode
210
Addressing Modes
10.Direct I/O port Addressing

Group IV : Addressing
modes for I/O ports
11.Indirect I/O port Addressing
211
Addressing Modes
Group V : Relative
12.Relative Addressing Addressing mode
212
Addressing Modes
Group VI : Implied
13.Implied Addressing Addressing mode
213
01/23/17
8086 Microprocessor Group I : Addressing modes for register and
Addressing Modes immediate data
1. Register Addressing Register Addressing

2. Immediate Addressing
The instruction will specify the name of the register which holds the
data to be operated by the instruction.
Example:
5. Based Addressing
MOV CL, DH

The content of 8-bit register DH is moved to another 8-bit register CL
8. Relative Based Indexed Addressing (CL)  (DH)
9. String Addressing
10. Direct I/O port Addressing
11. Indirect I/O port Addressing
12. Relative Addressing
13. Implied Addressing
215
8086 Microprocessor Group I : Addressing modes for register and
Addressing Modes immediate data
Immediate Addressing
1. Register Addressing
In immediate addressing mode, an 8-bit or 16-bit data is specified as
3. Direct Addressing part of the instruction
4. Register Indirect Addressing Example:

5. Based Addressing
MOV DL, 08H
The 8-bit data (08H) given in the instruction is moved to DL
(DL)  08H
MOV AX, 0A79FH
The 16-bit data (0A79FH) given in the instruction is moved to AX
register
(AX)  0A79FH
216
8086 Microprocessor
Addressing Modes : Memory Access
20 Address lines  8086 can address up to 220 = 1M bytes of

memory
However, the largest register is only 16 bits
Physical Address will have to be calculated Physical Address :

Actual address of a byte in memory. i.e. the value which goes out
onto the address bus.
Memory Address represented in the form – Seg : Offset

(Eg - 89AB:F012)
Each time the processor wants to access memory, it takes the

contents of a segment register, shifts it one hexadecimal place to the
left (same as multiplying by 1610), then add the required offset to
form the 20- bit address
16 bytes of contiguous memory
89AB : F012  89AB  89AB0 (Paragraph to byte  89AB x 10 = 89AB0)

F012  0F012 (Offset is already in byte unit)
+ -------
98AC2 (The 20-bit Physical address)
218
8086 Microprocessor
Addressing Modes Group II : Addressing modes for memory
data
1. Register Addressing Direct Addressing
Here, the effective address of the memory location at which the data
3. Direct Addressing operand is stored is given in the instruction.
The effective address is just a 16-bit number written directly in the
5. Based Addressing instruction.

6. Indexed Addressing Example:
7. Based Indexed Addressing MOV BX, [1354H]

MOV BL, [0400H]
9. String Addressing The square brackets around the 1354 H denotes the contents of the
memory location. When executed, this instruction will copy the
10. Direct I/O port Addressing contents of the memory location into BX register.
This addressing mode is called direct because the displacement of the
12. Relative Addressing operand from the segment base is specified directly in the instruction.
220
8086 Microprocessor Group II : Addressing modes for memory
Addressing Modes data
Register Indirect Addressing

In Register indirect addressing, name of the register which holds the
3. Direct Addressing effective address (EA) will be specified in the instruction.
4. Register Indirect Addressing Registers used to hold EA are any of the following registers:
5. Based Addressing
BX, BP, DI and SI.
Content of the DS register is used for base address calculation.
Example:
MOV CX, [BX] Note : Register/ memory enclosed in
9. String Addressing brackets refer to content of register/
memory
10. Direct I/O port Addressing Operations:
11. Indirect I/O port Addressing EA = (BX)

BA = (DS) x 1610
MA = BA + EA
(CX)  (MA) or,
(CL)  (MA)
(CH)  (MA +1)
221
1. Register Addressing Based Addressing
In Based Addressing, BX or BP is used to hold the base value for
3. Direct Addressing effective address.
5. Based Addressing
When BX holds the base value of EA, 20-bit physical address is
6. Indexed Addressing calculated from BX and DS.
7. Based Indexed Addressing When BP holds the base value of EA, BP and SS is used.
Example:
MOV AX, [BX]
11. Indirect I/O port Addressing Operations:

EA = (BX)
13. Implied Addressing BA = (DS) x 1610
MA = BA + EA
(AX)  (MA) or,
(AL)  (MA)
(AH)  (MA + 1)
222
Indexed Addressing
3. Direct Addressing SI or DI register is used to hold an index value for memory data.
4. Register Indirect Addressing The index value in SI or DI register is the EA.

5. Based Addressing
6. Indexed Addressing Example:
7. Based Indexed Addressing MOV CX, [SI]
8. Relative Based Indexed Addressing Operations:

EA = (SI)
10. Direct I/O port Addressing BA = (DS) x 1610
MA = BA + EA
(CX)  (MA) or,

(CL)  (MA)
(CH)  (MA + 1)
223
Based Indexed Addressing
3. Direct Addressing In Based Index Addressing, the effective address is computed from the
sum of a base register (BX or BP) and index register (SI or DI).
5. Based Addressing
Example:
MOV DX, [BX ][SI]
Operations:
9. String Addressing EA = (BX) + (SI)

BA = (DS) x 1610
10. Direct I/O port Addressing MA = BA + EA
(DX)  (MA) or,
(DL)  (MA)
13. Implied Addressing (DH)  (MA + 1)
224
1. Register Addressing Relative Based Indexed Addressing
In Relative Based Index Addressing, the effective address is computed
3. Direct Addressing from the sum of a base register (BX or BP), index register (SI or DI)
and 8-bit or 16-bit displacement.
5. Based Addressing Example:
6. Indexed Addressing MOV DX, [BX ][SI][2000H]

Operations:
EA = (BX) + (SI)+8-bit or 16-bit Disp.
BA = (DS) x 1610
10. Direct I/O port Addressing MA = BA + EA
11. Indirect I/O port Addressing (DX)  (MA) or,

(DL)  (MA)
13. Implied Addressing (DH)  (MA + 1)
225
8086 Microprocessor Group III : Addressing modes for string data
Addressing Modes
String Addressing
Employed in string operations to operate on string data.
The effective address (EA) of source data is stored in SI register and
4. Register Indirect Addressing the EA of destination is stored in DI register.
5. Based Addressing Segment register for calculating base address of

source data is DS and that of the destination data is ES

Example: MOVSB
Operations:
Calculation of source memory location:
EAD = (SI) BAD= (DS) x 1610 MAD = BAD + EAD
Calculation of destination memory location:
12. Relative Addressing EAE = (DI) BAE = (ES) x 1610 MAE = BAE + EAE
(MAE)  (MAD) Note : Effective address of the Extra
segment register
If DF = 1, then (SI)  (SI) – 1 and (DI) = (DI) - 1

If DF = 0, then (SI)  (SI) +1 and (DI) = (DI) + 1
226
8086 Microprocessor Group IV : Addressing modes for I/O
Addressing Modes ports
These addressing modes are used to access data from standard I/O
mapped devices or ports.
In Direct Port Addressing Mode, an 8-bit port address is directly
3. Direct Addressing specified in the instruction.
4. Register Indirect Addressing Example: IN AL, [09H]

5. Based Addressing
Operations: PORTaddr = 09H
6. Indexed Addressing (AL)  (PORT)
7. Based Indexed Addressing Content of port with address 09 H is moved to AL register

In Indirect Port Addressing Mode, the instruction will specify the name
9. String Addressing of the register which holds the port address. In 8086, the 16-bit port
address is stored in the DX register.
Example: OUT [DX], AX
Operations: PORTaddr = (DX)
(PORT)  (AX)
Content of AX is moved to port whose address is specified
by DX register.
227
8086 Microprocessor Group V : Relative Addressing mode
Addressing Modes
1. Register Addressing Relative Addressing
In this addressing mode, the effective address of a program
3. Direct Addressing instruction is specified relative to Instruction Pointer (IP) by an 8-bit
signed displacement.
5. Based Addressing Example: JZ 0AH
6. Indexed Addressing Operations:
7. Based Indexed Addressing 000AH  0AH (sign extend)

If ZF = 1, then
EA = (IP) + 000AH
10. Direct I/O port Addressing BA = (CS) x 1610
MA = BA + EA
12. Relative Addressing If ZF = 1, then the program control jumps to new address
calculated above.
If ZF = 0, then next instruction of the program is executed.
228
8086 Microprocessor Group VI : Implied Addressing mode
Addressing Modes
2. Immediate Addressing Implied Addressing
Instructions using this mode have no operands. The instruction itself
will specify the data to be operated by the instruction.
5. Based Addressing
Example: CLC
This clears the carry flag to zero.
229
8086 Microprocessor Instructions of 8086
 Program is a set of instructions written to

solve a problem.
 Instructions are the directions which a

microprocessor follows to execute a task or
part of a task.
 Broadly, computer language can be divided

into two parts as high-level language and
low level language.
 Low level language are machine specific.

 Low level language can be further divided into
machine language and assembly language.
 Machine language is the only language which a

machine can understand.
 Instructions in this language are written in

binary bits as a specific bit pattern. The
computer interprets this bit pattern as an
instruction to perform a particular task.
 The entire program is a sequence of binary

numbers.
 This is a machine-friendly language but not user

friendly.
 Debugging is another problem associated with

machine language.
 To overcome these problems, programmers
develop another way in which instructions are
written in English alphabets. This new language is
known as Assembly language.
 The instructions in this language are termed

mnemonics. As microprocessor can only understand
the machine language so mnemonics are translated
into machine language either manually or by a
program known as ‘ASSEMBLER’
 Efficient software development for the

microprocessor requires a complete familiarity
with the instruction set, their format and
addressing modes.
8086 Microprocessor Instruction Set
8086 supports 6 types of instructions
1. Data Transfer Instructions
2. Arithmetic Instructions
3. Logical Instructions
4. String manipulation Instructions
5. Control Transfer Instructions (Branching and

Looping Instructions)
6. Machine Control Instructions

233
8086 Microprocessor
Instruction Set

Instructions that are used to transfer data/ address in
to registers, memory locations and I/O ports.
Generally involve two operands: Source operand and

Destination operand of the same size.
Source: Register or a memory location or an

immediate data.
Destination : Register or a memory location.
The size should be a either a byte or a word.
A 8-bit data can only be moved to 8-bit register/

memory and a 16-bit data can be moved to 16-bit
register/ memory.
234
Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …
MOV reg2/ mem, reg1/ mem
MOV reg2, reg1 (reg2)  (reg1)

MOV mem, reg1 (mem)  (reg1)
MOV reg2, mem (reg2)  (mem)
MOV reg/ mem, data
MOV reg, data (reg)  data

MOV mem, data (mem)  data
XCHG reg2/ mem, reg1
XCHG reg2, reg1 (reg2)  (reg1)

XCHG mem, reg1 (mem)  (reg1)
235
PUSH reg/ mem
PUSH reg (SP)  (SP) – 2

MA S = (SS) x 1610 + SP
(MA S ; MA S + 1)  (reg16)
PUSH mem (SP)  (SP) – 2

MA S = (SS) x 1610 + SP
(MA S ; MA S + 1)  (mem)
POP reg/ mem
POP reg MA S = (SS) x 1610 + SP

(reg16)  (MA S ; MA S + 1)
(SP)  (SP) + 2
POP mem MA S = (SS) x 1610 + SP

(mem)  (MA S ; MA S + 1)
(SP)  (SP) + 2
236
IN AX, [DX] OUT [DX], AX
IN AL, [DX] PORTaddr = (DX) OUT [DX], AL PORTaddr = (DX)

(AL)  (PORT) (PORT)  (AL)
OUT [DX], AX
IN AX, [DX] PORTaddr = (DX) PORTaddr = (DX)
(AX)  (PORT) (PORT)  (AX)
OUT addr8, AX
IN AX, addr8
OUT addr8, AL (addr8)  (AL)
IN AL, addr8 (AL)  (addr8)
OUT addr8, AX (addr8)  (AX)
IN AX, addr8 (AX)  (addr8)
237
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
ADD reg2/ mem, reg1/mem
ADD reg2, reg1 (reg2)  (reg1) + (reg2)

ADD reg2, mem (reg2)  (reg2) + (mem)
ADD mem, reg1 (mem)  (mem)+(reg1)
ADD reg/mem, data
ADD reg, data (reg)  (reg)+ data

ADD mem, data (mem)  (mem)+data
ADD A, data
ADD AL, data8 (AL)  (AL) + data8

ADD AX, data16 (AX)  (AX) +data16
238
ADC reg2/ mem, reg1/mem
ADC reg2, reg1 (reg2)  (reg1) + (reg2)+CF

ADC reg2, mem (reg2)  (reg2) + (mem)+CF
ADC mem, reg1 (mem)  (mem)+(reg1)+CF
ADC reg/mem, data
ADC reg, data (reg)  (reg)+ data+CF

ADC mem, data (mem)  (mem)+data+CF
ADC A, data
ADC AL, data8 (AL)  (AL) + data8+CF

ADC AX, data16 (AX)  (AX) +data16+CF
239
SUB reg2/ mem, reg1/mem
SUB reg2, reg1 (reg2)  (reg1) - (reg2)

SUB reg2, mem (reg2)  (reg2) - (mem)
SUB mem, reg1 (mem)  (mem) - (reg1)
SUB reg/mem, data
SUB reg, data (reg)  (reg) - data

SUB mem, data (mem)  (mem) - data
SUB A, data
SUB AL, data8 (AL)  (AL) - data8

SUB AX, data16 (AX)  (AX) - data16
240
SBB reg2/ mem, reg1/mem
SBB reg2, reg1 (reg2)  (reg1) - (reg2) - CF

SBB reg2, mem (reg2)  (reg2) - (mem)- CF
SBB mem, reg1 (mem)  (mem) - (reg1) –CF
SBB reg/mem, data
SBB reg, data (reg)  (reg) – data - CF

SBB mem, data (mem)  (mem) - data - CF
SBB A, data
SBB AL, data8 (AL)  (AL) - data8 - CF

SBB AX, data16 (AX)  (AX) - data16 - CF
241
INC reg/ mem
INC reg8 (reg8)  (reg8) + 1
INC reg16 (reg16)  (reg16) + 1
INC mem (mem)  (mem) + 1
DEC reg/ mem
DEC reg8 (reg8)  (reg8) - 1
DEC reg16 (reg16)  (reg16) - 1
DEC mem (mem)  (mem) - 1
242
MUL reg/ mem UNSIGNED
MUL reg For byte : (AX)  (AL) x (reg8)

For word : (DX)(AX)  (AX) x (reg16)
MUL mem For byte : (AX)  (AL) x (mem8)

For word : (DX)(AX)  (AX) x (mem16)
IMUL reg/ mem SIGNED
IMUL reg For byte : (AX)  (AL) x (reg8)

For word : (DX)(AX)  (AX) x (reg16)
IMUL mem For byte : (AX)  (AX) x (mem8)

For word : (DX)(AX)  (AX) x (mem16)
243
DIV reg/ mem UNSIGNED
DIV reg For 16-bit :- 8-bit :

(AL)  (AX) :- (reg8) Quotient
(AH)  (AX) MOD(reg8) Remainder
For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (reg16) Quotient
(DX)  (DX)(AX) MOD(reg16) Remainder
DIV mem For 16-bit :- 8-bit :

(AL)  (AX) :- (mem8) Quotient
(AH)  (AX) MOD(mem8) Remainder

(AX)  (DX)(AX) :- (mem16) Quotient
(DX)  (DX)(AX) MOD(mem16) Remainder
244
IDIV reg/ mem SIGNED
IDIV reg For 16-bit :- 8-bit :

(AL)  (AX) :- (reg8) Quotient
(AH)  (AX) MOD(reg8) Remainder

(AX)  (DX)(AX) :- (reg16) Quotient
(DX)  (DX)(AX) MOD(reg16) Remainder
IDIV mem For 16-bit :- 8-bit :

(AL)  (AX) :- (mem8) Quotient
(AH)  (AX) MOD(mem8) Remainder

(AX)  (DX)(AX) :- (mem16) Quotient
(DX)  (DX)(AX) MOD(mem16) Remainder
245
CMP reg2/mem, reg1/ mem
CMP reg2, reg1 Modify flags  (reg2) – (reg1)
If (reg2) > (reg1) then CF=0, ZF=0, SF=0

If (reg2) < (reg1) then CF=1, ZF=0, SF=1
If (reg2) = (reg1) then CF=0, ZF=1, SF=0
CMP reg2, mem Modify flags  (reg2) – (mem)
If (reg2) > (mem) then CF=0, ZF=0, SF=0

If (reg2) < (mem) then CF=1, ZF=0, SF=1
If (reg2) = (mem) then CF=0, ZF=1, SF=0
CMP mem, reg1 Modify flags  (mem) – (reg1)
If (mem) > (reg1) then CF=0, ZF=0, SF=0

If (mem) < (reg1) then CF=1, ZF=0, SF=1
If (mem) = (reg1) then CF=0, ZF=1, SF=0
246
CMP reg/mem, data

CMP reg, data Modify flags  (reg) – (data)
If (reg) > data then CF=0, ZF=0, SF=0

If (reg) < data then CF=1, ZF=0, SF=1
If (reg) = data then CF=0, ZF=1, SF=0
CMP mem, data Modify flags  (mem) – (mem)
If (mem) > data then CF=0, ZF=0, SF=0

If (mem) < data then CF=1, ZF=0, SF=1
If (mem) = data then CF=0, ZF=1, SF=0
CMP A, data
CMP AL, data8 Modify flags  (AL) – data8
If (AL) > data8 then CF=0, ZF=0, SF=0

If (AL) < data8 then CF=1, ZF=0, SF=1
If (AL) = data8 then CF=0, ZF=1, SF=0
CMP AX, data16 Modify flags  (AX) – data16
If (AX) > data16 then CF=0, ZF=0, SF=0

If (mem) < data16 then CF=1, ZF=0, SF=1
If (mem) = data16 then CF=0, ZF=1, SF=0 247
Few More....
 AAA (ASCII Adjust after Addition):
 The data entered from the terminal is in ASCII
format.
 In ASCII, 0 – 9 are represented by 30H – 39H.
 This instruction allows us to add the ASCII codes.
 This instruction does not have any operand.
Other ASCII Instructions:
 AAS (ASCII Adjust after Subtraction)
 AAM (ASCII Adjust after Multiplication)
 AAD (ASCII Adjust Before Division)
248
Few More....
DAA (Decimal Adjust after Addition):
 It is used to make sure that the result of adding
two BCD numbers is adjusted to be a correct BCD
number.
 It only works on AL register.
DAS (Decimal Adjust after Subtraction):
 It is used to make sure that the result of

subtracting two BCD numbers is adjusted to be a
correct BCD number.
 It only works on AL register.
249
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, ROL, RCR …








4. String Manipulation Instructions
 String : Sequence of bytes or words
 8086 instruction set includes instruction for string movement,

comparison, scan, load and store.
 REP instruction prefix : used to repeat execution of string

instructions
 String instructions end with S or SB or SW, where (S represents

string, SB string byte and SW string word)
 Offset or effective address of the source operand is stored in SI

register and that of the destination operand is stored in DI register.
 Depending on the status of DF, SI and DI registers are automatically

updated.
 DF = 0 || SI and DI are incremented by 1 for byte and 2 for word.
 DF = 1 || SI and DI are decremented by 1 for byte and 2 for word.

Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS
REP
REPZ/ REPE While CX  0 and ZF = 1, repeat

execution of string instruction
(Repeat CMPS or SCAS until ZF = 0) and
(CX)  (CX) – 1
REPNZ/ REPNE
(Repeat CMPS or SCAS until ZF = 1) While CX  0 and ZF = 0, repeat

execution of string instruction
and
(CX)  (CX) - 1
MOVS
MOVSB MA = (DS) x 1610 + (SI)

MAE = (ES) x 1610 + (DI)
(MAE)  (MA)
If DF = 0, then (DI)  (DI) + 1; (SI)  (SI) + 1

If DF = 1, then (DI)  (DI) - 1; (SI)  (SI) - 1
MOVSW
MA = (DS) x 1610 + (SI)
MAE = (ES) x 1610 + (DI)
(MAE ; MAE + 1)  (MA; MA + 1)

CMPS
CMPSB MA = (DS) x 1610 + (SI)

MAE = (ES) x 1610 + (DI)
Modify flags  (MA) - (MAE)
If (MA) > (MAE), then CF = 0; ZF = 0; SF = 0

CMPSW If (MA) < (MAE), then CF = 1; ZF = 0; SF = 1
If (MA) = (MAE), then CF = 0; ZF = 1; SF = 0
For byte operation

For word operation

SCAS
SCASB MAE = (ES) x 1610 + (DI)

Modify flags  (AL) - (MAE)
If (AL) > (MAE), then CF = 0; ZF = 0; SF = 0

If (AL) < (MAE), then CF = 1; ZF = 0; SF = 1
If (AL) = (MAE), then CF = 0; ZF = 1; SF = 0
If DF = 0, then (DI)  (DI) + 1

If DF = 1, then (DI)  (DI) – 1
SCASW
MAE = (ES) x 1610 + (DI)
Modify flags  (AL) - (MAE)
If (AX) > (MAE ; MAE + 1), then CF = 0; ZF = 0; SF = 0

If (AX) < (MAE ; MAE + 1), then CF = 1; ZF = 0; SF = 1
If (AX) = (MAE ; MAE + 1), then CF = 0; ZF = 1; SF = 0
If DF = 0, then (DI)  (DI) + 2

LODS
LODSB MA = (DS) x 1610 + (SI)

(AL)  (MA)
If DF = 0, then (SI)  (SI) + 1

If DF = 1, then (SI)  (SI) – 1
LODSW MA = (DS) x 1610 + (SI)

(AX)  (MA ; MA + 1)
If DF = 0, then (SI)  (SI) + 2

If DF = 1, then (SI)  (SI) – 2
STOS
STOSB MAE = (ES) x 1610 + (DI)

(MAE)  (AL)
If DF = 0, then (DI)  (DI) + 1

If DF = 1, then (DI)  (DI) – 1
STOSW MAE = (ES) x 1610 + (DI)

(MAE ; MAE + 1 )  (AX)
If DF = 0, then (DI)  (DI) + 2

If DF = 1, then (DI)  (DI) – 2
5. Control Transfer Instructions
(Branching and Looping Instructions)
Also known as Program Execution transfer Instructions
 8086 Unconditional Transfers
 8086 Conditional Transfers

 8086 Signed Conditional Transfers
 8086 Unsigned Conditional Transfers
8086 Unconditional Transfers

 Transfer the control to a specific destination or target
instruction
 Do not affect flags
Mnemonics Explanation
CALL reg/ mem/ disp16 Call subroutine
RET Return from

subroutine
JMP reg/ mem/ disp8/ disp16 Unconditional jump
8086 Conditional Transfers

 Checks flags
 If conditions are true, the program control is
transferred to the new memory location in the same
segment by modifying the content of IP

Signed Conditional Transfers Unsigned Conditional Transfers
Name Alternate name Name Alternate name
JG disp8 JNLE disp8 JA disp8 JNBE disp8

Jump if greater Jump if not less or Jump if above Jump if not below
equal or equal
JGE disp8 JNL disp8 JAE disp8 JNB disp8

Jump if greater Jump if not less Jump if above or Jump if not below
than or equal equal
JL disp8 JNGE disp8 JB disp8 JNAE disp8

Jump if less than Jump if not greater Jump if below Jump if not above
than or equal or equal
JLE disp8 JNG disp8 JBE disp8 JNA disp8

Jump if less than Jump if not greater Jump if below or Jump if not above
or equal equal

8086 conditional
Carry
branch JC disp8 Jump if CF = 1
instructions JNC disp8 Jump if CF = 0
responding with JP disp8 Jump if PF = 1
respect to the JNP disp8 Jump if PF = 0
condition/status JO disp8 Jump if OF = 1
of status flags JNO disp8 Jump if OF = 0
JS disp8 Jump if SF = 1
JNS disp8 Jump if SF = 0
JZ disp8 Jump if result is zero, i.e, ZF = 1
JNZ disp8 Jump if result is not zero, i.e, ZF = 0


8086 conditional
Parity


8086 conditional
condition/status JO disp8 Jump if OF = 1 Overflow


8086 conditional
JS disp8 Jump if SF = 1 Sign


8086 conditional

Zero


8086 conditional
Carry
Parity
condition/status JO disp8 Jump if OF = 1 Overflow
JS disp8 Jump if SF = 1 Sign

Zero

6. Machine Control Instructions

Also known as STC Set CF  1
Processor Control CLC Clear CF  0
Instructions CMC Complement carry CF  CF/
STD Set direction flag DF  1
CLD Clear direction flag DF  0

These instructions
STI Set interrupt enable flag IF  1
are used to control
CLI Clear interrupt enable flag IF 
the processor action 0
by setting/resetting NOP No operation
the flag values and HLT Halt after interrupt is set
also contains WAIT Wait for TEST pin active
instructions which ESC Used to pass instruction to a

directly affect opcode
mem/ reg
coprocessor which shares the
address and data bus with the
processor 8086
LOCK Lock bus during next instruction
Assembler
Directives
8086 Microprocessor Assemble Directives
 Hints/Commands to the Assembler regarding the

program being executed.
 Control the generation of machine codes and

organization of the program; but no machine codes
are generated for assembler directives.
 Also called ‘pseudo instructions’
 Used to :
 specify the start and end of a program
 attach value to variables
 allocate storage locations to input/ output data
 define start and end of segments, procedures,
macros etc..
8086 Microprocessor
Assemble Directives
DB EQU
DW PROC
SEGMENT ENDP
ENDS FAR
ASSUME NEAR
ORG SHORT
END MACRO
EVEN ENDM
278
DB  Define Byte
DW
 Define a byte type (8-bit) variable
ASSUME
SEGMENT
 Reserves specific amount of memory locations to each variable
ENDS
 Range : 00H – FFH for unsigned value; 00H – 7FH for positive
ORG
END value and 80H – FFH for negative value
EVEN
EQU
General form : variable DB value/ values
PROC
ENDP
FAR Example:
NEAR
LIST DB 7FH, 42H, 35H
SHORT
MACRO Three consecutive memory locations are reserved for the

ENDM variable LIST and each data specified in the instruction are
stored as initial value in the reserved memory location
DB  Define Word
DW
 Define a word type (16-bit) variable
ASSUME
SEGMENT
ENDS
 Reserves two consecutive memory locations to each variable
ORG
END
 Range : 0000H – FFFFH for unsigned value;
EVEN 0000H – 7FFFH for positive value and 8000H – FFFFH for
EQU
negative value
PROC
ENDP
FAR General form : variable DW value/ values
NEAR
Example:
SHORT
MACRO ALIST DW 6512H, 0F251H, 0CDE2H

ENDM
Six consecutive memory locations are reserved for the
variable ALIST and each 16-bit data specified in the
instruction is stored in two consecutive memory location.
DB  Informs the assembler the name of the program/ data

DW segment that should be used for a specific segment.
ASSUME
General form
SEGMENT
ENDS
ASSUME segreg : segnam, .. , segreg : segnam
ORG
END
EVEN
EQU User defined name of the
Segment Register
segment
PROC
ENDP
FAR
NEAR
Example:
SHORT
ASSUME CS: CODE, DS:DATA Tells the compiler that the instructions of
MACRO the program are stored in the segment
ENDM CODE and data are stored in the segment
DATA
DB  SEGMENT : Used to indicate the beginning of a code/

DW data/Extra/ stack segment
ASSUME
 ENDS : Used to indicate the end of a code/ data/Extra/ stack
SEGMENT
ENDS
segment
ORG
END
General form
EVEN
EQU Segnam SEGMENT
PROC … Program code

ENDP … or
FAR … Data Defining Statements
NEAR …
…
SHORT
…
MACRO
ENDM Segnam ENDS
User defined name of the

segment
 ORG (Origin) is used to assign the starting address (Effective address) for a
DB
program(code)/ data segment
DW
 END is used to terminate a program; statements after END will be ignored
ASSUME
SEGMENT  EVEN : Informs the assembler to store the program instructions/ data in the
ENDS memory address starting from an even address
ORG
END  EQU (Equate) is used to attach a value to a variable
EVEN
EQU Example:
ORG 1000H Informs the assembler that the statements
PROC
ENDP
following ORG 1000H should be stored in
FAR memory starting with effective address 1000H
NEAR
SHORT
Var EQU 10FEH Value of variable Var is 10FEH
MACRO
ENDM
DATA SEGMENT In this data segment, effective address of
ORG 1200H memory location assigned to A will be 1200H
A DB 4CH
and that of B will be 1202H and 1203H.
EVEN
B DW 1052H
DATA ENDS
DB
 PROC Indicates the beginning of a procedure
DW
 ENDP End of procedure
ASSUME
SEGMENT  FAR Intersegment call

ENDS
ORG  NEAR Intrasegment call

END
EVEN
EQU Example:
procname PROC [NEAR/ FAR]
PROC
ENDP
… Program statements of the
FAR
NEAR
… procedure
…
SHORT Last statement of the procedure
RET
MACRO
ENDM
procname ENDP
procedure
DB
 Reserves one memory location for 8-bit signed
DW displacement in jump instructions
ASSUME
SEGMENT
ENDS
ORG
END
EVEN
EQU Example:
PROC
ENDP
FAR JMP SHORT The directive will reserve one memory
NEAR AHEAD location for 8-bit displacement named
AHEAD
SHORT
MACRO
ENDM
DB
 MACRO Indicate the beginning of a macro
DW
ASSUME  ENDM End of a macro

SEGMENT
ENDS
ORG
END
EVEN
EQU Example:
PROC
ENDP macroname MACRO [Arg1, Arg2 ...]
FAR Program statements in the
NEAR … macro
SHORT
…
…
MACRO
ENDM ENDM

macro
8086 Microprocessor
Macros
 Writing a macro is one way of ensuring
modular programming in assembly language.
A macro is a sequence of instructions, assigned
by a name and could be used anywhere in the
program.
 Modular Programming is a software design

technique that emphasizes separating the
functionality of a program into independent,
interchangeable modules, such that each
contains everything necessary to execute only
one aspect of the desired functionality.
8086 Microprocessor
Macros Verses Procedures
 PROCEDUREs and MACROs are two different

constructs that reduces the number of errors
in your program by reducing the lines in your
program
8086 Microprocessor

8086 Microprocessor

8086 Microprocessor

8086 Microprocessor
Sample Programs
Addition using Immediate Addressing

8086 Microprocessor
Sample Programs
Addition using Indexed Addressing
8086 Microprocessor
Sample Programs
Sorting of an Array
8086 Microprocessor
Sample Programs
Strings Comparison Program
End of Lecture
Thank You
Queries?
*Discussion*

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Unit– 1

Vikas Kumar Tiwari

of bus & memory.

To study the basic concepts of Advanced ARM processors

Understands the internal architecture, organization and assembly

language programming of 8086 processors.

Understands the internal architecture, organization and assembly

language programming of 8051/controllers

Understands the interfacing techniques to 8086 and 8051 based

Understands the internal architecture of ARM processors and basic

concepts of advanced ARM processors.

Unit- 2 Introduction to Microcontrollers; About the internal architecture, organization

Unit- 4 ARM Architecture About the internal architecture of ARM

Unit- 2 Introduction to Microcontrollers; About the internal architecture, organization

Unit- 4 ARM Architecture About the internal architecture of ARM

Unit- 2 Introduction to Microcontrollers; About the internal architecture, organization

Unit- 4 ARM Architecture About the internal architecture of ARM

Unit- 2 Introduction to Microcontrollers; About the internal architecture, organization

Unit- 4 ARM Architecture About the internal architecture of ARM

Unit- 2 Introduction to Microcontrollers; About the internal architecture, organization

Unit- 4 ARM Architecture About the internal architecture of ARM

Unit- 2 Introduction to Microcontrollers; About the internal architecture, organization

Unit- 4 ARM Architecture About the internal architecture of ARM

Instruction Set and

Assembly Language Programming of

It is used as CPU (Central Processing Unit)

Intel 8085 (8 bit processor) 18

Intel 8086 (16 bit processor)

Originally HMOS, now manufactured

Approximately 29,000 transistors, 40-

Does not have internal clock; external

20-bit address to access memory 

Originally HMOS, now manufactured

Approximately 29,000 transistors, 40-

Does not have internal clock; external

20-bit address to access memory 

Originally HMOS, now manufactured

Approximately 29,000 transistors, 40-

Does not have internal clock; external

20-bit address to access memory 

Originally HMOS, now manufactured

Approximately 29,000 transistors, 40-

Does not have internal clock; external

20-bit address to access memory 

Originally HMOS, now manufactured

Approximately 29,000 transistors, 40-

Does not have internal clock; external

20-bit address to access memory 

Originally HMOS, now manufactured

Approximately 29,000 transistors, 40-

Does not have internal clock; external

20-bit address to access memory 

Originally HMOS, now manufactured

Approximately 29,000 transistors, 40-

Does not have internal clock; external

20-bit address to access memory 

Originally HMOS, now manufactured

Approximately 29,000 transistors, 40-

Does not have internal clock; external

20-bit address to access memory 

Bus Interface Unit (BIU)

BIU fetches instructions, reads data