INTERCONNECTION

NETWORKS
Today’s Agenda

1. Introduction to Interconnection Networks

2. Terminologies
3. Topologies
4. Analysis

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1. INTRODUCTION
TO
INTERCONNECTION
NETWORKS

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Where is interconnect used?
 To connect components.
 To make communication possible within components.

Interconnection network

•Processors and processors

•Processors and memories
•Processors and caches
•Caches and caches
•I/O devices

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Interconnection between two devices

 Two end nodes ; Direct Connection

 Interconnection network behaves as dedicated
links.
 Request, reply

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Interconnection between multiple devices

 Interconnection Network: Topology

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Why is it important?

 Affects the scalability of the system

 How large of a system can you build?
 How easily can you add more processors?

 Affects performance and energy efficiency

 How fast can processors, caches, and memory
communicate?
 How long are the latencies to memory?
 How much energy is spent on communication?

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Goal

 To provide
 Low latency
 High data Transfer rate
 Wide communication Bandwidth
 Interconnect Networks should be designed to
transfer the maximum amount of information within
the least amount of time, cost, and power
constraints so as not to bottleneck the system.

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2. TERMINOLOGIES

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Basic Network Structures and Functions

 Composing and processing messages, packets

 Packet Transport
 Reliable delivery (Flow control) and error handling

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Additional Network Structure

 Topology
 What paths are possible for packets?
 Indicates how the nodes of network are organized.

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Additional Network Functions
 Routing
 Which of the possible paths are allowable (valid) for packets?
 Provides the set of operations needed to compute a valid path.
 Executed at source, intermediate, or even at destination nodes.
 Routing determines the path that will conduct packets from source
to destination. This process must take into account traffic, path
length as well as division of labor in calculating the route.

 Arbitration
 When paths are available for packets? (along with Flow Control)
 Resolves packets requesting the same resources at the same
time.
 For every arbitration, there is a winner and possibly many losers.
 Losers are buffered (lossless) or dropped on overflow
(lossy).

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Additional Network Functions

 Switching
 How are paths allocated to packets?
 The winning packet (from arbitration) proceeds towards
destination
 Switching is similar to routing; it must perform the task of
configuring connection(s) in order to transmit packets.
Switching techniques:
 Circuit switching (similar to the telephone system) which
reserves a path for the transmission of packets
 Packet switching in which each packet may use a different
path to its destination (no guarantees on the order either).

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Routing

 The routing algorithm of a network determines

which of the possible paths from source to
destination are used as routes.
 Determine the route followed by each particular
packet

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Routing

 The key properties of good routing

algorithms
 set of deadlock-free routes
 maintaining low latency
 spreading load evenly
 tolerating faults

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Types of Routing Algorithm

 Deterministic
Always choose the same path for a communicating source
destination pair.

 Oblivious
Chooses different paths, without considering network state.

 Adaptive
Can choose different paths, adapting to the state of the
network.

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Arbitration

 Performed at each switch, regardless of topology

 Determines use of paths supplied to packets
 Needed to resolve conflicts for shared resources by
requestors
 Ideally:
Maximize the matching between available network
resources and packets requesting them
 At the switch level, arbiters maximize the matching of free
switch output ports and packets located at switch input ports.

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Arbitration

Problems: Starvation
 Arises when packets can never gain access to
requested resources
 Solution: Grant resources to packets with
fairness, even if prioritized

Many straightforward distributed arbitration techniques

for switches
 Two-phased arbiters, three-phased arbiters, and
iterative arbiters

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Metrics
 Degree
Number of links (edges) per node.

 Diameter
Longest distance between two nodes in the network. The
distance is measured in terms of number of distinct hops
between any two nodes.

 Cost
Number of links

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Metrics

 Latency
Delay in transferring message between two nodes

 Bandwidth
Maximum transfer rate between two nodes

 Throughput
Total number of messages that a network can transfer per
unit time

 Scalability
Ability of Expansion

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3. TOPOLOGIES

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Taxonomy

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Static Vs Dynamic Networks

 Static Network:
 The connection between nodes are fixed and cannot be
changed.
 Cannot be reconfigured.
 They are used to build computers where communication
pattern is more or less fixed.

 Dynamic Network:
 Enable changing (Reconfiguring) of the connection
structure in a system.

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Degree 1: Shared Bus Topology

 Simplest type of static network, has a degree of 1.

 Least expensive network to implement.
 Nodes can be easily added or deleted from this network. It
requires a mechanism for handling conflict when several nodes
request the bus simultaneously.
 This mechanism can be achieved through a bus controller,
which gives access to the bus either on a first-come, first-
served basis or through a priority scheme.

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Degree 1: Shared Bus Topology

 The shared bus has a diameter of 1 since each

node can access the other nodes through the
shared bus.

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Degree 2: Linear Array

 Has (degree of 2) each node connected with two neighbors (except

the far ends nodes).

 Long communication delays, especially between far-end nodes

 A linear array, with N nodes, has a diameter of N-1.

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Degree 2: Ring Topology
 A ring network has a degree of 2. Similar to the linear
array, each node is connected to two of its neighbors,
 Ring can be unidirectional or bidirectional. In a
unidirectional ring, the data can travel in only one
direction.Such a ring has a diameter of N-1, like the
linear array.
 If a node fail, the other direction can be used to
complete a message transmission.

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Degree 2: Ring Topology

 A bidirectional ring network’s reliability, as compared

to the linear array, is improved.

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Degree 3: Binary Tree
 In the tree interconnection network, processors are
arranged in a complete binary tree pattern.
 The binary tree has the advantages of being expandable
and having a simple implementation.
 A packet is routed upward toward the root node until it
reaches a destination node.
 It can still cause long communication delays between far
away leaf nodes. Leaf nodes farthest away from each
other must ultimately pass their message through the
root.

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Degree 3: Binary Tree
 Since traffic increases as the root is
approached, bottleneck issue.

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Degree 3: Fat Tree
 It is a modified version of tree network.
 In this bandwidth of edge increases towards root.
 Bottleneck problem is avoided in this type of tree
because of higher bandwidth.
 One problem with the binary tree is that there can be
heavy traffic toward the root node. To reduce the effect
of such a problem, the fat tree was proposed.
 Proceeding up from the leaf nodes of a fat tree to the
root, the number of communication links increases, and
therefore the communication bandwidth increases.

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 Degree 3: Fat Tree
 Each edge of the binary tree corresponds to two channels
of the fat tree. The number of communication links in each
channel increases as we go up the tree from the leaves.

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Varying Degree: Cube

 Special d-dimensional mesh.

 PE’s are arranged in this structure.
 d = log p ; p = 2d

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 Hyper Cube

 Extension of cube network for d>3

 16 nodes; 24 = 16; d=4 (4 dimensional cube)

+ Low Latency
- Hard to lay out

• Used in some
early message
passing machines:
o Intel iPSC
o nCube

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 Single Bus Systems

+ Use of local cache reduces Limited Bandwidth

traffic. One processor can access
the bus
+ Size varies between 2 and 50
processors One memory access can
take place at any given time.

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Multiple Bus Systems

 Several parallel buses to interconnect multiple

processors and multiple memory modules.
 Many connection schemes are possible:

 Multiple Bus with Full Bus – Memory Connection

(MBFBMC)
 Multiple Bus with Single Bus – Memory Connection
(MBSBMC)
 Multiple Bus with Partial Bus – Memory Connection
(MBPBMC)
 Multiple Bus with Class-based Bus – Memory Connection
(MBCBMC)

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Multiple Bus Systems: MBFBMC

 Multiple Bus with Full Bus – Memory Connection

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Multiple Bus Systems: MBSBMC

 Multiple Bus with Single Bus – Memory Connection

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Multiple Bus Systems: MBPBMC

 Multiple Bus with Partial Bus - Memory Connection

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Multiple Bus Systems: MBCBMC

 Multiple Bus with Class-based Memory Connection

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Single Stage Switch-based Network

 Single Stage of Switching Element (SE) exists between the inputs

and outputs of the Network.
Input: Processors
 Possible settings of 2x2 SE: Output: Memory banks

 If number of input = n , number of output = n, then number of SE

in a stage = n/2.
 Examples:
 Shuffle Exchange Network
 Butterfly Network
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Single Stage Shuffle Exchange Network

 Direct Topology
 Obtained by shuffling left most bit to right side.

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Single Stage Butterfly Network

 Direct Topology
 Obtained by interchanging the MSB in address with LSB.

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Multi Stage Switch-based Network
 Limitation of Single Stage: availability of only one path
between source and destination modules.
 Solution: Multi stages having set of SE in each stage.
 Stages are connected to each other using inter-stage
connection (ISC) pattern.
 Routing of message based

on destination address
(Self-routing).
 Examples:
 Omega Network
 Banyan Network

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Multi stage network: Omega Network

 Multi stage version of Shuffle Exchange Network

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Multi stage network: Banyan Network

 Each stage use inverse shuffle permutation.

 Shuffle right most bit to left side.

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Crossbar

 Every node connected to all other nodes. (mxn grid)

 Good for small number of nodes

+ Low Latency
+ High Throughput
Expensive
Not Scalable easily
Difficult to arbitrate
 Applications:
 IBM Power5
 Sun Niagara I/II

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4. ANALYSIS

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Analysis of Static Networks

Degree Diameter Latency Bisection Cost

Width

Linear 2 N-1 N 1 N-1

Array

Ring N N

Tree 3 2 log n Log n 1 N-1

Hypercube Log n Log n Log n n/2

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Analysis of Dynamic Networks
Degree Diameter Latency Bisection Cost
Width

Single Bus N 1

Multiple mN M
Bus
Shuffle 2 2 log n -1 N / log n
Exchange
Butterfly 4 Log n N/ 2

Omega N/ 2 N log n

Crossbar 1 n n2

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