Stick Diagrams

 VLSI design aims to translate circuit concepts

onto silicon.
 Stick diagrams are a means of capturing
topography and layer information using simple
diagrams.
 Stick convey layer information
diagrams
through colour codes (or monochrome
 encoding).
Acts as an interface between symbolic
circuit
and the actual layout.

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 Stick Diagrams
Does not show
 Exact placement of components/vias.
 Transistor sizes
 Wire lengths, wire widths, tub boundaries.
 Any other low level details such as parasitics..
 Goes one step closer to the layout

A stick diagram is a cartoon of a layout.

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 Stick Diagrams – Colour Notations

Metal 1

poly

ndif

f
Can also draw
in shades of
pdif gray/line style.

f
Similarly for contacts, via, tub etc..
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Stick Diagrams – Some rules
Rule 1.
 When two or more ‘sticks’ of the same type
cross or touch each other that represents
electrical contact.

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 Stick Diagrams – Some rules

Rule 2.
 When two or more ‘sticks’ of different type cross or
touch each other there is no electrical contact.
(If electrical contact is needed we have to show the connection
explicitly).

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 Stick Diagrams – Some rules

Rule 3.
 When a poly crosses diffusion it represents a
transistor.

Note: If a contact is shown then it is not a transistor

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 Stick Diagrams – Some rules

Rule 4.
 In CMOS a demarcation line is drawn to avoid
touching of p-diff with n-diff. All pMOS must lie on
one side of the line and all nMOS will have to be on
the other side.

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Example: NMOS
Transistor

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Stick diagram
 Stick diagrams help to plan layout quickly
 Need not be to scale
 Draw with color pencils or dry-erase markers

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How to draw Stick Diagrams -
CMOS Inverter (Two Version)

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Draw the stick diagram for
the following expression

y  (a  b) 
c

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Draw the stick diagram for
the following expression

y  (a  b) 
c
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Stick Diagram using Euler’s Graph

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Euler Path

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Connection label layout

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VDD, VSS and Output Labels

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Find out logic function

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Find out logic function

Out = (A(B+C) + DE)’

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 Euler’s path
Determine the path such that PUN and PDN should give same path.

All the transistors in PUN and PDN are covered.

Each transistor should be crossed/covered once only

Vdd
a
1
b c PDN path : a b c f e d / b c a d e f / d e f c b a
2
d e f
Y
a b d

c e

f
gnd 35
 y  a  (b  c)  (d  e  y (b  c)  a  (d  e 
f) f)

Vdd Vdd
a b c
1 1
b c a

2 2
d e f d e f
Y Y
a b d a b d
3
c e c e
4
f f
gnd gnd

PUN path : b c a d e f PDN path : b c a d e f

Euler’s path : b c a d e f 36
 y  (b  c)  a  (d  e 
f) Vdd Vdd
b c b c a d e f
1 P diff
a
Y
2
d e f
Y
a b d
5 3
c e 3 4
4 5 N diff
f
gnd gnd

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Optimize the stick diagram for
e = (a + bc + d)*(f +g)

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Optimize the stick diagram for
e = (a + bc + d)*(f +g)

Euler’s path = (d, g, f, a, b, c)

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