ECET 111

Introduction to Digital System Design I

 Chapter 5
Sequential Logic Circuits
 Latches
 Flip-flops
 Analysis
 State reduction
 Design
 Introduction
Sequential Circuit
consists of a combinational circuit to which storage
elements are connected to form a feedback path
Thus, a sequential circuit is specified by a time sequence of
inputs, outputs, and internal states .
 Flip-Flop
The most important memory element in the sequential
circuit is the flip-flop, which is made up of an
assembly of logic gates.
 Flip-Flop
The most important memory element in the sequential
circuit is the flip-flop, which is made up of an
assembly of logic gates.

Page 192
Clocked SR Flip-flop
S

R
 Clocked SR Flip-flop
S Q
En
Q’
R
 Clocked SR Flip-flop
S Q
En
Q’
R
 Clock Signals and Clocked Flip-flops
When the clock changes from a 0 to a 1, this is called the Positive Edge clock
When the clock changes from a 1 to a 0, this is called the Negative Edge clock
 Clock Signals and Clocked Flip-flops
When the clock changes from a 0 to a 1, this is called the Positive Edge clock
When the clock changes from a 1 to a 0, this is called the Negative Edge clock

Positive Edge Negative Edge

 Clocked SR Flip-flop

Positive Edge
Clocked SR Flip-flop

Positive Edge
Clocked SR Flip-flop

Positive Edge
Clocked SR Flip-flop

Positive Edge
Clocked SR Flip-flop

Positive Edge
 Clocked SR Flip-flop Positive Edge

                                                                     

                                                                   

                                                                     

                                                                   

                                                                     

Clk                                                                    

                                                                     

                                                                   

                                                                     

                                                                   
 Clocked SR Flip-flop Positive Edge

                                                                     

                                                                   

                                                                     

                                                                   

                                                                     

Clk                                                                    

                                                                     

                                                                   

                                                                     

                                                                   
 Clocked SR Flip-flop

Negative Edge
 Clocked SR Flip-flop Negative Edge

                                                                     

                                                                   

                                                                     

                                                                   

                                                                     

Clk                                                                    

                                                                     

                                                                   

                                                                     

                                                                   
 Clocked SR Flip-flop Negative Edge

                                                                     

                                                                   

                                                                     

                                                                   

                                                                     

Clk                                                                    

                                                                     

                                                                   

                                                                     

                                                                   
 Clocked JK Flip-flop

Positive Edge
 Clocked JK Flip-flop Positive Edge

                                                                     

                                                                   

                                                                     

                                                                   

                                                                     

Clk                                                                    

                                                                     

                                                                   

                                                                     

                                                                   
 Clocked JK Flip-flop Negative Edge

                                                                     

                                                                   

                                                                     

                                                                   

                                                                     

Clk                                                                    

                                                                     

                                                                   

                                                                     

                                                                   
 Clocked JK Flip-flop Positive Edge

                                                                     

                                                                   

                                                                     

                                                                   

                                                                     

Clk                                                                    

                                                                     

                                                                   

                                                                     

                                                                   
Clocked D Flip-flop
Clocked D Flip-flop
Clocked D Flip-flop
Clocked D Flip-flop
 Clocked D Flip-flop Negative Edge

                                                                     

                                                                   

                                                                     

Clk                                                                    

                                                                     

                                                                   

                                                                     

                                                                   
Clocked T Flip-flop
 Clocked T Flip-flop Negative Edge

                                                                     

                                                                   

                                                                     

Clk                                                                    

                                                                     

                                                                   

                                                                     

                                                                   
 Clocked T Flip-flop Negative Edge

                                                                     

                                                                   

                                                                     

Clk                                                                    

                                                                     

                                                                   

                                                                     

                                                                   
 Clocked JK Flip-flop

Positive Edge
Clocked D Flip-flop
Clocked D Flip-flop
Clocked T Flip-flop
Sequential Circuit With
D flip-flop
Sequential Circuit With
D flip-flop
Example
Derive the state table and
the state diagram of the
sequential circuit shown
Sequential Circuit With
D flip-flop

State Equations
Sequential Circuit With
D flip-flop
State Table
State Equations
Sequential Circuit With
D flip-flop
State Table
State Equations
Sequential Circuit With
D flip-flop
State Table
State Diagram
Sequential Circuit With
JK flip-flop
Example
Derive the state equations,
state table and the state diagram
of the sequential circuit shown
Sequential Circuit With Pages 212, 213, 214, 215
JK flip-flop
State Equations
Sequential Circuit With Pages 212, 213, 214, 215
JK flip-flop
State Equations
Sequential Circuit With State Table
JK flip-flop
Present State Flip-flop Inputs Next State
State Equations
A B x JA KA JB KB A B
Sequential Circuit With
State Table
JK flip-flop
Present State Flip-flop Inputs Next State
State Equations
A B x JA KA JB KB A B
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Sequential Circuit With
State Table
JK flip-flop
Present State Flip-flop Inputs Next State
State Equations
A B x JA KA JB KB A B
0 0 0 0 0 1 0
0 0 1 0 0 0 1
0 1 0 1 1 1 0
0 1 1 1 0 0 1
1 0 0 0 0 1 1
1 0 1 0 0 0 0
1 1 0 1 1 1 1
1 1 1 1 0 0 0
Sequential Circuit With
State Table
JK flip-flop
Present State Flip-flop Inputs Next State
State Equations
A B x JA KA JB KB A B
0 0 0 0 0 1 0 0 1
0 0 1 0 0 0 1 0 0
0 1 0 1 1 1 0 1 1
0 1 1 1 0 0 1 1 0
1 0 0 0 0 1 1 1 1
1 0 1 0 0 0 0 1 0
1 1 0 1 1 1 1 0 0
1 1 1 1 0 0 0 1 1
Sequential Circuit With
State Table
JK flip-flop
Present State Flip-flop Inputs Next State
State Diagram
A B x JA KA JB KB A B
0 0 0 0 0 1 0 0 1
0 0 1 0 0 0 1 0 0
0 1 0 1 1 1 0 1 1
0 1 1 1 0 0 1 1 0
1 0 0 0 0 1 1 1 1
1 0 1 0 0 0 0 1 0
1 1 0 1 1 1 1 0 0
1 1 1 1 0 0 0 1 1
Sequential Circuit With
State Table
JK flip-flop
Present State Next State
State Diagram
A B x A B
0 0 0 0 1
0 0 1 0 0
0 1 0 1 1
0 1 1 1 0
1 0 0 1 1
1 0 1 1 0
1 1 0 0 0
1 1 1 1 1
Sequential Circuit With
JK flip-flop
Sequential Circuit With State Equations
T flip-flop
Sequential Circuit With
T flip-flop
State Equations
Sequential Circuit With
T flip-flop
Present State Flip-flop Next Output State Equations
Inputs State
A B x TA TB A B Y
Sequential Circuit With
T flip-flop
Present State Flip-flop Next Output State Equations
Inputs State
A B x TA TB A B Y
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Sequential Circuit With
T flip-flop
Present State Flip-flop Next Output State Equations
Inputs State
A B x TA TB A B Y
0 0 0 0 0
0 0 1 0 1
0 1 0 0 0
0 1 1 1 1
1 0 0 0 0
1 0 1 0 1
1 1 0 0 0
1 1 1 1 1
Sequential Circuit With
T flip-flop
Present State Flip-flop Next Output State Equations
Inputs State
A B x TA TB A B Y
0 0 0 0 0 0 0
0 0 1 0 1 0 1
0 1 0 0 0 0 1
0 1 1 1 1 1 0
1 0 0 0 0 1 0
1 0 1 0 1 1 1
1 1 0 0 0 1 1
1 1 1 1 1 0 0
Sequential Circuit With
T flip-flop
Present State Flip-flop Next Output State Equations
Inputs State
A B x TA TB A B Y
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 1 0 0 0 0 1 0
0 1 1 1 1 1 0 0
1 0 0 0 0 1 0 0
1 0 1 0 1 1 1 0
1 1 0 0 0 1 1 1
1 1 1 1 1 0 0 1
Problem

Positive Edge
Present State Input Flip-flops Inputs Next State
A B x JA KA JB KB A B
 Lecture Outline
• Flip-flops (Review)
• Analysis of Clocked Sequential Circuits
– State Equations
– State Diagram
– State Table
 Clocked JK Flip-flop

Positive Edge
Clocked D Flip-flop
Clocked T Flip-flop
Sequential Circuit With
JK flip-flop
Example
Derive the state table and the state
diagram of the sequential circuit shown
𝑱 𝑨=¿ 𝑲 𝑨=¿

𝑱 𝑩 =¿ 𝑲 𝑩 =¿

𝑱 𝑪 =¿ 𝑲 𝑪 =¿

𝒚=¿
Sequential Circuit With
JK flip-flop
Example
Derive the state table and the state
diagram of the sequential circuit shown
𝑱 𝑨 =𝒙 ′ 𝑲 𝑨 =𝑩

𝑱 𝑩 =𝒙𝑨 𝑲 𝑩 =𝑪

𝑱 𝑪= 𝑨 𝑲 𝑪 =𝒙

𝒚= 𝒙+ 𝑩 ′
Sequential Circuit With
JK flip-flop
Example
Derive the state table and the state
diagram of the sequential circuit shown
𝑱 𝑨 =𝒙 ′ 𝑲 𝑨 =𝑩
𝑨 ( 𝒕 +𝟏 ) = 𝑱 𝑨 ′ + 𝑲 ′ 𝑨=𝒙 ′ 𝑨 ′ + 𝑨𝑩′
𝑱 𝑩 =𝒙𝑨 𝑲 𝑩 =𝑪

𝑩 ( 𝒕 +𝟏 )= 𝑱 𝑩′ + 𝑲 ′ 𝑩= 𝒙𝑨 𝑩 ′ + 𝑩𝑪 ′
𝑱 𝑪= 𝑨 𝑲 𝑪 =𝒙

𝑪 ( 𝒕 +𝟏 )= 𝑱 𝑪′ + 𝑲 ′ 𝑪= 𝑨 𝑪 ′ + 𝒙 ′ 𝑪
𝒚= 𝒙+ 𝑩 ′
 Present State Input Flip-flops Inputs Next State Output
A B C x JA KA JB KB JC KC A B C y
0 0 0 0
0 0 0 1

𝑱 𝑨 =𝒙 ′ 𝑲 𝑨 =𝑩 0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1

𝑱 𝑩 =𝒙𝑨 𝑲 𝑩 =𝑪 0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
𝑱 𝑪= 𝑨 𝑲 𝑪 =𝒙
1 0 1 1
1 1 0 0
1 1 0 1

𝒚= 𝒙+ 𝑩 ′ 1 1 1 0
1 1 1 1
 Present State Input Flip-flops Inputs Next State Output
A B C x JA KA JB KB JC KC A B C y
0 0 0 0 1 0
0 0 0 1 0 0

𝑱 𝑨 =𝒙 ′ 𝑲 𝑨 =𝑩 0 0 1 0 1 0
0 0 1 1 0 0
0 1 0 0 1 1
0 1 0 1 0 1

𝑱 𝑩 =𝒙𝑨 𝑲 𝑩 =𝑪 0 1 1 0 1 1
0 1 1 1 0 1
1 0 0 0 1 0
1 0 0 1 0 0
1 0 1 0 1 0
𝑱 𝑪= 𝑨 𝑲 𝑪 =𝒙
1 0 1 1 0 0
1 1 0 0 1 1
1 1 0 1 0 1

𝒚= 𝒙+ 𝑩 ′ 1 1 1 0 1 1
1 1 1 1 0 1
 Present State Input Flip-flops Inputs Next State Output
A B C x JA KA JB KB JC KC A B C y
0 0 0 0 1 0 0
0 0 0 1 0 0 0

𝑱 𝑨 =𝒙 ′ 𝑲 𝑨 =𝑩 0 0 1 0 1 0 0
0 0 1 1 0 0 0
0 1 0 0 1 1 0
0 1 0 1 0 1 0

𝑱 𝑩 =𝒙𝑨 𝑲 𝑩 =𝑪 0 1 1 0 1 1 0
0 1 1 1 0 1 0
1 0 0 0 1 0
1 0 0 1 0 0
1 0 1 0 1 0
𝑱 𝑪= 𝑨 𝑲 𝑪 =𝒙
1 0 1 1 0 0
1 1 0 0 1 1
1 1 0 1 0 1

𝒚= 𝒙+ 𝑩 ′ 1 1 1 0 1 1
1 1 1 1 0 1
 Present State Input Flip-flops Inputs Next State Output
A B C x JA KA JB KB JC KC A B C y
0 0 0 0 1 0 0
0 0 0 1 0 0 0

𝑱 𝑨 =𝒙 ′ 𝑲 𝑨 =𝑩 0 0 1 0 1 0 0
0 0 1 1 0 0 0
0 1 0 0 1 1 0
0 1 0 1 0 1 0

𝑱 𝑩 =𝒙𝑨 𝑲 𝑩 =𝑪 0 1 1 0 1 1 0
0 1 1 1 0 1 0
1 0 0 0 1 0 0
1 0 0 1 0 0 1
1 0 1 0 1 0 0
𝑱 𝑪= 𝑨 𝑲 𝑪 =𝒙
1 0 1 1 0 0 1
1 1 0 0 1 1 0
1 1 0 1 0 1 1

𝒚= 𝒙+ 𝑩 ′ 1 1 1 0 1 1 0
1 1 1 1 0 1 1
 Present State Input Flip-flops Inputs Next State Output
A B C x JA KA JB KB JC KC A B C y
0 0 0 0 1 0 0 0
0 0 0 1 0 0 0 0

𝑱 𝑨 =𝒙 ′ 𝑲 𝑨 =𝑩 0 0 1 0 1 0 0 1
0 0 1 1 0 0 0 1
0 1 0 0 1 1 0 0
0 1 0 1 0 1 0 0

𝑱 𝑩 =𝒙𝑨 𝑲 𝑩 =𝑪 0 1 1 0 1 1 0 1
0 1 1 1 0 1 0 1
1 0 0 0 1 0 0 0
1 0 0 1 0 0 1 0
1 0 1 0 1 0 0 1
𝑱 𝑪= 𝑨 𝑲 𝑪 =𝒙
1 0 1 1 0 0 1 1
1 1 0 0 1 1 0 0
1 1 0 1 0 1 1 0

𝒚= 𝒙+ 𝑩 ′ 1 1 1 0 1 1 0 1
1 1 1 1 0 1 1 1
 Present State Input Flip-flops Inputs Next State Output
A B C x JA KA JB KB JC KC A B C y
0 0 0 0 1 0 0 0 0
0 0 0 1 0 0 0 0 0

𝑱 𝑨 =𝒙 ′ 𝑲 𝑨 =𝑩 0 0 1 0 1 0 0 1 0
0 0 1 1 0 0 0 1 0
0 1 0 0 1 1 0 0 0
0 1 0 1 0 1 0 0 0

𝑱 𝑩 =𝒙𝑨 𝑲 𝑩 =𝑪 0 1 1 0 1 1 0 1 0
0 1 1 1 0 1 0 1 0
1 0 0 0 1 0 0 0 1
1 0 0 1 0 0 1 0 1
1 0 1 0 1 0 0 1 1
𝑱 𝑪= 𝑨 𝑲 𝑪 =𝒙
1 0 1 1 0 0 1 1 1
1 1 0 0 1 1 0 0 1
1 1 0 1 0 1 1 0 1

𝒚= 𝒙+ 𝑩 ′ 1 1 1 0 1 1 0 1 1
1 1 1 1 0 1 1 1 1
 Present State Input Flip-flops Inputs Next State Output
A B C x JA KA JB KB JC KC A B C y
0 0 0 0 1 0 0 0 0 0
0 0 0 1 0 0 0 0 0 1

𝑱 𝑨 =𝒙 ′ 𝑲 𝑨 =𝑩 0 0 1 0 1 0 0 1 0 0
0 0 1 1 0 0 0 1 0 1
0 1 0 0 1 1 0 0 0 0
0 1 0 1 0 1 0 0 0 1

𝑱 𝑩 =𝒙𝑨 𝑲 𝑩 =𝑪 0 1 1 0 1 1 0 1 0 0
0 1 1 1 0 1 0 1 0 1
1 0 0 0 1 0 0 0 1 0
1 0 0 1 0 0 1 0 1 1
1 0 1 0 1 0 0 1 1 0
𝑱 𝑪= 𝑨 𝑲 𝑪 =𝒙
1 0 1 1 0 0 1 1 1 1
1 1 0 0 1 1 0 0 1 0
1 1 0 1 0 1 1 0 1 1

𝒚= 𝒙+ 𝑩 ′ 1 1 1 0 1 1 0 1 1 0
1 1 1 1 0 1 1 1 1 1
 Present State Input Flip-flops Inputs Next State Output
A B C x JA KA JB KB JC KC A B C y
0 0 0 0 1 0 0 0 0 0 1
0 0 0 1 0 0 0 0 0 1 0

𝑱 𝑨 =𝒙 ′ 𝑲 𝑨 =𝑩 0 0 1 0 1 0 0 1 0 0 1
0 0 1 1 0 0 0 1 0 1 0
0 1 0 0 1 1 0 0 0 0 1
0 1 0 1 0 1 0 0 0 1 0

𝑱 𝑩 =𝒙𝑨 𝑲 𝑩 =𝑪 0 1 1 0 1 1 0 1 0 0 1
0 1 1 1 0 1 0 1 0 1 0
1 0 0 0 1 0 0 0 1 0 1
1 0 0 1 0 0 1 0 1 1 1
1 0 1 0 1 0 0 1 1 0 1
𝑱 𝑪= 𝑨 𝑲 𝑪 =𝒙
1 0 1 1 0 0 1 1 1 1 1
1 1 0 0 1 1 0 0 1 0 0
1 1 0 1 0 1 1 0 1 1 0

𝒚= 𝒙+ 𝑩 ′ 1 1 1 0 1 1 0 1 1 0 0
1 1 1 1 0 1 1 1 1 1 0
 Present State Input Flip-flops Inputs Next State Output
A B C x JA KA JB KB JC KC A B C y
0 0 0 0 1 0 0 0 0 0 1 0 0 1
0 0 0 1 0 0 0 0 0 1 0 0 0 1

𝑱 𝑨 =𝒙 ′ 𝑲 𝑨 =𝑩 0 0 1 0 1 0 0 1 0 0 1 0 1 1
0 0 1 1 0 0 0 1 0 1 0 0 0 1
0 1 0 0 1 1 0 0 0 0 1 1 0 0
0 1 0 1 0 1 0 0 0 1 0 1 0 1

𝑱 𝑩 =𝒙𝑨 𝑲 𝑩 =𝑪 0 1 1 0 1 1 0 1 0 0 1 0 1 0
0 1 1 1 0 1 0 1 0 1 0 0 0 1
1 0 0 0 1 0 0 0 1 0 1 0 1 1
1 0 0 1 0 0 1 0 1 1 1 1 1 1
1 0 1 0 1 0 0 1 1 0 1 0 1 1
𝑱 𝑪= 𝑨 𝑲 𝑪 =𝒙
1 0 1 1 0 0 1 1 1 1 1 1 0 1
1 1 0 0 1 1 0 0 1 0 0 1 1 0
1 1 0 1 0 1 1 0 1 1 0 1 1 1

𝒚= 𝒙+ 𝑩 ′ 1 1 1 0 1 1 0 1 1 0 0 0 1 0
1 1 1 1 0 1 1 1 1 1 0 0 0 1
 Present State Input Next State Output
A B C x A B C y
0 0 0 0 1 0 0 1
0 0 0 1 0 0 0 1
0 0 1 0 1 0 1 1
𝑱 𝑨 =𝒙 ′ 𝑲 𝑨 =𝑩
0 0 1 1 0 0 0 1
0 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1

𝑱 𝑩 =𝒙𝑨 𝑲 𝑩 =𝑪 0 1 1 0 1 0 1 0
0 1 1 1 0 0 0 1
1 0 0 0 1 0 1 1
1 0 0 1 1 1 1 1
1 0 1 0 1 0 1 1
𝑱 𝑪= 𝑨 𝑲 𝑪 =𝒙
1 0 1 1 1 1 0 1
1 1 0 0 0 1 1 0
1 1 0 1 0 1 1 1
1 1 1 0 0 0 1 0
𝒚= 𝒙+ 𝑩 ′
1 1 1 1 0 0 0 1
 Present State Input Flip-flops Inputs Next State Output
A B C x JA KA JB KB JC KC A B C y
0 0 0 0 1 0 0 0 0 0 1 0 0
0 0 0 1 0 0 0 0 0 1 0 0 0

𝑱 𝑨 =𝒙 ′ 𝑲 𝑨 =𝑩 0 0 1 0 1 0 0 1 0 0 1 0 1
0 0 1 1 0 0 0 1 0 1 0 0 0
0 1 0 0 1 1 0 0 0 0 1 1 0
0 1 0 1 0 1 0 0 0 1 0 1 0

𝑱 𝑩 =𝒙𝑨 𝑲 𝑩 =𝑪 0 1 1 0 1 1 0 1 0 0 1 0 1
0 1 1 1 0 1 0 1 0 1 0 0 0
1 0 0 0 1 0 0 0 1 0 1 0 1
1 0 0 1 0 0 1 0 1 1 1 1 1
1 0 1 0 1 0 0 1 1 0 1 0 1
𝑱 𝑪= 𝑨 𝑲 𝑪 =𝒙
1 0 1 1 0 0 1 1 1 1 1 1 0
1 1 0 0 1 1 0 0 1 0 0 1 1
1 1 0 1 0 1 1 0 1 1 0 1 1

𝒚= 𝒙+ 𝑩 ′ 1 1 1 0 1 1 0 1 1 0 0 0 1
1 1 1 1 0 1 1 1 1 1 0 0 0
 Present State Input Next State Output
A B C x A B C y
0 0 0 0 1 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 1 0 1 0

000 100 0
0
0
1
1
0
1
0
0
1
0
1
0
0
1
0
0 1 0 1 0 1 0 0
0 1 1 0 1 0 1 0

111 101 0 1 1 1 0 0 0 0
1 0 0 0 1 0 1 0
1 0 0 1 1 1 1 1
001 1 0 1 0 1 0 1 0
1 0 1 1 1 1 0 1

010 1
1
1
1
0
0
0
1
0
0
1
1
1
1
0
0
110 1 1 1 0 0 0 1 0
011 1 1 1 1 0 0 0 0
 Problem
A sequential circuit has two T flip-flops A and B, one input x and
one output Y .
The flip-flop input equations and circuit output equation are:

a) Draw the Logic diagram of the Circuit.

b) Drive the state equations.
c) Tabulate the state table
d) Draw the state diagram
 Flip-flops Problems
Number of States =
Number of Rows =

Analysis Design
Givens Circuit or State Equations State Diagram or State Table
Unknown State Table/State Diagram State Equations/Circuit
Table State Table Excitation Table
 Lecture Outline
• Flip-flops (Review)
• Clocked Sequential Circuits Design
– State Equations
– State Diagram
– State Table
 Design
Design a sequential circuit with two D Flip-flop
A and B and one input xin
When xin= 0, the state of the circuit remains the same.
When xin= 1, the circuit goes through the transition from
00 to 01 to 11 to 10 back to 00 and repeats.
 Design
Present State Input Next State
I/P
A B Xin A B
 Design
Present State Input Next State
I/P
A B Xin A B
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
 Design
Present State Input Next State
I/P
A B Xin A B
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 1
1 0 0 1 0
1 0 1 0 0
1 1 0 1 1
1 1 1 1 0
 Design
Present State Input Next State
I/P
A B Xin A B
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 1
1 0 0 1 0
1 0 1 0 0
1 1 0 1 1
1 1 1 1 0
 Design
Present State Input Next State
I/P
A B Xin A B
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 1
1 0 0 1 0
1 0 1 0 0
1 1 0 1 1
1 1 1 1 0
 Design
Design a sequential circuit with two T Flip-flop
A and B and one input xin
When xin= 0, the state of the circuit remains the same.
When xin= 1, the circuit goes through the transition from
00 to 01 to 11 to 10 back to 00 and repeats.
 Design
Present Input Next A B
State I/P State Flip- Flip-flop
flop
A B Xin A B TA TB
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 1
1 0 0 1 0
1 0 1 0 0
1 1 0 1 1
1 1 1 1 0
 Design
Present Input Next A B
State I/P State Flip- Flip-flop
flop
A B Xin A B TA TB
0 0 0 0 0 TExcitation Table
0 0 1 0 1
0 1 0 0 1 Qt Qt+1 T
0 1 1 1 1 0 0 0
1 0 0 1 0
1 0 1 0 0
0 1 1
1 1 0 1 1 1 0 1
1 1 1 1 0
1 1 0
 Design
Present Input Next A B
State I/P State Flip- Flip-flop
flop
A B Xin A B TA TB
0 0 0 0 0 0 0 TExcitation Table
0 0 1 0 1 0 1
0 1 0 0 1 0 0 Qt Qt+1 T
0 1 1 1 1 1 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 0 1 0
0 1 1
1 1 0 1 1 0 0 1 0 1
1 1 1 1 0 0 1
1 1 0
 Design
Design a sequential circuit with two JK Flip-flop
A and B and one input xin
When xin= 0, the state of the circuit remains the same.
When xin= 1, the circuit goes through the transition from
00 to 01 to 11 to 10 back to 00 and repeats.
 Design
Present Inpu A B
State t Next State Flip-flop Flip-flop
I/P
A B Xin A B JA KA JB KB
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 1
1 0 0 1 0
1 0 1 0 0
1 1 0 1 1
1 1 1 1 0
 Design
Present Inpu A B
State t Next State Flip-flop Flip-flop
I/P
A B Xin A B JA KA JB KB
0 0 0 0 0 JK Excitation Table
0 0 1 0 1
0 1 0 0 1 Qt Qt+1 J K
0 1 1 1 1 0 0
1 0 0 1 0
1 0 1 0 0
0 1
1 1 0 1 1 1 0
1 1 1 1 0
1 1
 Design
Present Inpu A B
State t Next State Flip-flop Flip-flop
I/P
A B Xin A B JA KA JB KB
0 0 0 0 0 JK Excitation Table
0 0 1 0 1
0 1 0 0 1 Qt Qt+1 J K
0 1 1 1 1 0 0 0 X
1 0 0 1 0
1 0 1 0 0
0 1 1 X
1 1 0 1 1 1 0 X 1
1 1 1 1 0
1 1 X 0
 Design
Present Inpu A B
State t Next State Flip-flop Flip-flop
I/P
A B Xin A B JA KA JB KB
0 0 0 0 0 JK Excitation Table
0 0 1 0 1
0 1 0 0 1 Qt Qt+1 J K
0 1 1 1 1 0 0 0 X
1 0 0 1 0
1 0 1 0 0
0 1 1 X
1 1 0 1 1 1 0 X 1
1 1 1 1 0
1 1 X 0
 Design
Present Inpu A B
State t Next State Flip-flop Flip-flop
I/P
A B Xin A B JA KA JB KB
0 0 0 0 0 JK Excitation Table
0 0 1 0 1
0 1 0 0 1 Qt Qt+1 J K
0 1 1 1 1 0 0 0 X
1 0 0 1 0
1 0 1 0 0
0 1 1 X
1 1 0 1 1 1 0 X 1
1 1 1 1 0
1 1 X 0
 Design
Present Inpu A B
State t Next State Flip-flop Flip-flop
I/P
A B Xin A B JA KA JB KB
0 0 0 0 0 0 X JK Excitation Table
0 0 1 0 1 0 X
0 1 0 0 1 0 X Qt Qt+1 J K
0 1 1 1 1 1 X 0 0 0 X
1 0 0 1 0 X 0
1 0 1 0 0 X 1
0 1 1 X
1 1 0 1 1 X 0 1 0 X 1
1 1 1 1 0 X 0
1 1 X 0
 Design
Present Inpu A B
State t Next State Flip-flop Flip-flop
I/P
A B Xin A B JA KA JB KB
0 0 0 0 0 0 X JK Excitation Table
0 0 1 0 1 0 X
0 1 0 0 1 0 X Qt Qt+1 J K
0 1 1 1 1 1 X 0 0 0 X
1 0 0 1 0 X 0
1 0 1 0 0 X 1
0 1 1 X
1 1 0 1 1 X 0 1 0 X 1
1 1 1 1 0 X 0
1 1 X 0
 Design
Present Inpu A B
State t Next State Flip-flop Flip-flop
I/P
A B Xin A B JA KA JB KB
0 0 0 0 0 0 X 0 X JK Excitation Table
0 0 1 0 1 0 X 1 X
0 1 0 0 1 0 X X 0 Qt Qt+1 J K
0 1 1 1 1 1 X X 0 0 0 0 X
1 0 0 1 0 X 0 0 X
1 0 1 0 0 X 1 0 X
0 1 1 X
1 1 0 1 1 X 0 X 0 1 0 X 1
1 1 1 1 0 X 0 X 1
1 1 X 0
 Design
Present Inpu A B
State t Next State Flip-flop Flip-flop
I/P
A B Xin A B JA KA JB KB
0 0 0 0 0 0 X 0 X JK Excitation Table
0 0 1 0 1 0 X 1 X
0 1 0 0 1 0 X X 0 Qt Qt+1 J K
0 1 1 1 1 1 X X 0 0 0 0 X
1 0 0 1 0 X 0 0 X
1 0 1 0 0 X 1 0 X
0 1 1 X
1 1 0 1 1 X 0 X 0 1 0 X 1
1 1 1 1 0 X 0 X 1
1 1 X 0
 Design
Present Inpu A B
State t Next State Flip-flop Flip-flop
I/P
A B Xin A B JA KA JB KB
0 0 0 0 0 0 X 0 X JK Excitation Table
0 0 1 0 1 0 X 1 X
0 1 0 0 1 0 X X 0 Qt Qt+1 J K
0 1 1 1 1 1 X X 0 0 0 0 X
1 0 0 1 0 X 0 0 X
1 0 1 0 0 X 1 0 X
0 1 1 X
1 1 0 1 1 X 0 X 0 1 0 X 1
1 1 1 1 0 X 0 X 1
1 1 X 0
 Design
Design a sequential circuit with two T Flip-flops
A and B and one input xin
When xin= 0, the state of the circuit remains the same.
When xin= 1, the circuit goes through the transition from
00 to 01 to 11 to 10 back to 00 and repeats.
 Design
Present Inpu Flip-flops
State t Next State Input
I/P
A B Xin A B TA TB
0 0 0 0 0 0 0 T Excitation Table
0 0 1 0 1 0 1
0 1 0 0 1 0 0 Qt Qt+1 T
0 1 1 1 1 1 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 0 1 0
0 1 1
1 1 0 1 1 0 0 1 0 1
1 1 1 1 0 0 1
1 1 0
Problem
Design a sequential circuit using three D Flip-flops
(positive edge) A, B and C; one input Xin and one
output Yout. The Sate Diagram as shown.
The Circuit is to be designed by treating the unused
states as don’t care conditions.
a) Tabulate the state table.
b) Solve the K-Maps to find the flip-flops input
equations.
c) Draw the circuit diagram.
d) Complete the timing diagram.
Present State Input Next State Output
A B C Xin A B C Yout 0/1
0/1
0 0 0 0 0 0 0 1
0 0 0 1 0 1 0 1
0 0 1 0 0 0 1 1 001 1/0
110
0 0 1 1 1 0 0 1
0 1 0 0 0 1 1 1 1/1 0/0
0 1 0 1 1 0 0 1 1/0
0 1 1 0 0 0 1 0
0 1 1 1 1 1 0 0 1/1
100 011
1 0 0 0 0 0 0 0 1/1
0/0 0/1
1 0 0 1 0 1 1 1
1 0 1 0 X X X X
1 0 1 1 X X X X 000
1 1 0 0 1 1 0 1 1/1
0/1
1 1 0 1 0 0 1 1
1 1 1 0 X X X X 1/1
1 1 1 1 X X X X
010
Problem
Design a sequential circuit using three JK Flip-flops
(positive edge) A, B and C; one input Xin and one
output Yout. The Sate Diagram as shown.
The Circuit is to be designed by treating the unused
states as don’t care conditions.
a) Tabulate the state table.
b) Solve the K-Maps to find the flip-flops input
equations.
c) Draw the circuit diagram.
d) Complete the timing diagram.
Present Next Outpu
Input JK FF Inputs
State State t
A B C Xin A B C Yout JA KA JB KB JC KC
0 0 0 0 0 0 0 1 0 X
0 0 0 1 0 1 0 1 0 X
0 0 1 0 0 0 1 1 0 X
0 0 1 1 1 0 0 1 1 X
0 1 0 0 0 1 1 1 0 X
0 1 0 1 1 0 0 1 1 X Qt Qt+1 J K
0 1 1 0 0 0 1 0 0 X
0 1 1 1 1 1 0 0 1 X 0 0 0 X
1 0 0 0 0 0 0 0 X 1
1 0 0 1 0 1 1 1 X 1 0 1 1 X
1 0 1 0 X X X X X X X X X X
1 0 1 1 X X X X X X X X X X 1 0 X 1
1 1 0 0 1 1 0 1 X 0
1 1 0 1 0 0 1 0 X 1 1 1 X 0
1 1 1 0 X X X X X X X X X X
1 1 1 1 X X X X X X X X X X
Problem
Design a sequential circuit using three T Flip-flops
(positive edge) A, B and C; one input Xin and one
output Yout. The Sate Diagram as shown.
The Circuit is to be designed by treating the unused
states as don’t care conditions.
a) Tabulate the state table.
b) Solve the K-Maps to find the flip-flops input
equations.
c) Draw the circuit diagram.
d) Complete the timing diagram.
Present Next
State
Input
State
Output T Flipflop
A B C Xin A B C Yout TA TB TC
0 0 0 0 0 0 0 1 0 0 0
0 0 0 1 0 1 0 1 0 1 0
0 0 1 0 0 0 1 1 0 0 0
0 0 1 1 1 0 0 1 1 0 1
0 1 0 0 0 1 1 1 0 0 1
0 1 0 1 1 0 0 1 1 1 0
0 1 1 0 0 0 1 0 0 1 0
0 1 1 1 1 1 0 0 1 0 1 T Excitation Table
1 0 0 0 0 0 0 0 1 0 0
1 0 0 1 0 1 1 1 1 1 1 Qt Qt+1 T
1 0 1 0 x x x X X X X
1 0 1 1 x x x X X X X 0 0 0
1 1 0 0 1 1 0 1 0 0 0
1 1 0 1 0 0 1 0 1 1 1 0 1 1
1 1 1 0 x x x X X X X
1 1 1 1 x x x X X X X 1 0 1
1 1 0
 Timing Diagram
                                       
0/1 0/1
                                     

                                       
1/0
001 110
Clk                                      
1/1 0/0
                                       
1/0
                                     
1/1
100 011
                                       
0/0 0/1 1/1
                                     

                                      1/1 000
0/1
1/1

010
 Outlines
• Review
– Four‐Bits Shift Register
– Four‐Bits Shift Register Applications
– Serial Transfer
• Four‐bit universal shift register
• Ripple Counters
• BCD Ripple Counters
 Flip-flops Problems
Number of States =
Number of Rows =

Analysis Design
Givens Circuit or State Equations State Diagram or State Table
Unknown State Table/State Diagram State Equations/Circuit
Table State Table Excitation Table
 Find The Logic Expression of F
𝑭 ( 𝒘 , 𝒙 , 𝒚 , 𝒛 )=( 𝒘 ( 𝒘 + 𝒙 )) . ( ( 𝒙 . 𝒛 ) + 𝒚  )
not
𝒘
𝒘 𝒘 𝒘 (𝒘 +𝒙 )
𝒙 OR 𝒘 +𝒙
NAND

not
𝒚 AND

𝒙 𝒚 ( 𝒙 . 𝒛 ) +𝒚  

𝒛 AND 𝒙 . 𝒛
NOR
 Two Variables K-Map
Example 2
Find K-Map and Simplify

Step 1: Put F in Standard Form

 Two Variables K-Map
Example 2 𝒚
𝒚 𝒚 0 1
𝒙
𝑭 =𝒙+𝒚 0
m0 m1

𝒙 𝒙
m2 m3
1