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Digital Signal Processing: Unit-Vi
Digital Signal Processing: Unit-Vi
UNIT-VI
Prof. V. N. Bhonge
Dept. of Electronics & Telecomm.
Shri Sant Gajanan Maharaj College of Engg,
Shegaon – 444203
vnbhonge@gmail.com
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Multirate Digital Signal
Processing
UNIT-VI
Multirate Digital Signal Processing: Sampling,
Sampling rate conversion, signal flow graph, filter
structure, polyphase decomposition, digital filter
design, multilevel filter bank. Overview and
architecture of DSP processor TMS320C54XX.
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Prof. V. N. Bhonge Dept. of E & T
What does multirate mean?
•Multirate simply means “multiple sampling rates”.
• A multirate DSP system uses multiple sampling rates within
the system.
•Whenever a signal at one rate has to be used by a system that
expects a different rate, the rate has to be increased or decreased,
and some processing is required to do so.
•Therefore “Multirate DSP” really refers to the art or science
of changing sampling rates.
The process of converting a signal from a given rate to
a different rate is called sampling rate conversion.
System that employ multiple sampling rates in the
processing of digital signals are called multirate
digital signal processing systems.
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Why should I do multirate DSP?
The most immediate reason is when you need to pass
data between two systems which use incompatible
sampling rates.
For example,
Professional audio systems use 48 kHz rate, but consumer CD
players use 44.1 kHz , for broadcasting 32 KHz; when audio
professionals transfer their recorded music to CDs, they need to
do a rate conversion.
But the most common reason is that multirate DSP can greatly
increase processing efficiency which reduces DSP system cost.
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Multirate Digital Signal Processing
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Up-Sampler
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Up-Sampler
Figure below shows the up-sampling by a factor of 3 of a
sinusoidal sequence with a frequency of 0.12 Hz obtained.
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Up-Sampler
• In practice, the zero-valued samples inserted by
the up-sampler are replaced with appropriate
nonzero values using some type of filtering
process
• Process is called interpolation and will be
discussed later
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Down-Sampler
Time-Domain Characterization
• An down-sampler with a down-sampling
factor M, where M is a positive integer,
develops an output sequence y[n] with a
sampling rate that is (1/M)-th of that of the
input sequence x[n]
• Block-diagram representation
x[n] M y[n]
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Down-Sampler
• Down-sampling operation is implemented
by keeping every M-th sample of x[n] and
removing M 1 in-between samples to
generate y[n]
• Input-output relation
y[n] = x[nM]
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Down-Sampler
• Figure below shows the down-sampling by
a factor of 3 of a sinusoidal sequence of
frequency 0.042 Hz.
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Basic Sampling Rate Alteration
Devices
• Sampling periods have not been explicitly
shown in the block-diagram representations
of the up-sampler and the down-sampler
• This is for simplicity and the fact that the
mathematical theory of multirate systems
can be understood without bringing the
sampling period T or the sampling
frequency FT into the picture
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Down-Sampler
x[ n ] xa ( nT ) M y[ n ] xa ( nMT )
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Up-Sampler
x[ n ] xa ( nT ) L y[n]
x ( nT / L ), n 0, L, 2 L,
a
0 otherwise
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Basic Sampling Rate Alteration
Devices
• Consider a factor-of-M down-sampler
defined by y[n] = x[nM]
• Its output y1[n] for an input x1[n] x[n n0 ]
is then given by
y1[n] x1[ Mn] x[ Mn n0 ]
• From the input-output relation of the down-
sampler we obtain
y[n n0 ] x[ M (n n0 )]
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x[ Mn Mn0 ] y1[n]
Up-Sampler
Frequency-Domain Characterization
• Consider first a factor-of-2 up-sampler
whose input-output relation in the time-
domain is given by
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Spectrum of the Up-Sampler
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Cont…
j
• On the unit circle, for z e , the input-
output relation is given by
j j L
X u (e ) X (e )
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Cont…
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Up-Sampler
• As can be seen, a factor-of-2 sampling rate
j
expansion leads to a compression of X (e )
by a factor of 2 and a 2-fold repetition in
the baseband [0, 2]
• This process is called imaging as we get an
additional “image” of the input spectrum
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Up-Sampler
• Similarly in the case of a factor-of-L
sampling rate expansion, there will be L 1
additional images of the input spectrum in
the baseband
• Lowpass filtering of xu [n] removes the L 1
images and in effect “fills in” the zero-
valued samples in xu [n] with interpolated
sample values
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Up-Sampler
• Illustrate the frequency-domain properties
of the up-sampler shown below for L = 4
0.6
Magnitude
0.6
0.4 0.4
0.2 0.2
0 0
0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1
w/p w/p
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Spectrum of the Down-Sampler
Frequency-Domain Characterization
• Applying the z-transform to the input-output
relation of a factor-of-M down-sampler
y[n] x[Mn]
we get
n
Y ( z) x[Mn] z
n
• The expression on the right-hand side cannot be
directly expressed in terms of X(z)
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Cont…
• To get around this problem, define a new
sequence xint [n] :
x[n], n 0, M , 2 M ,
xint [n]
0, otherwise
• Then
n n
Y ( z) x[Mn] z xint [Mn] z
n n
k / M 1/ M
xint [k ] z X int ( z )
28 k
Cont…
• Now, xint [n] can be formally related to x[n]
through
xint [n] c[n] x[n]
where
1, n 0, M , 2 M ,
c[n]
0, otherwise
• A convenient representation of c[n] is given
by 1 M 1 kn
c[n]
M k 0
WM
where WM e j 2 / M
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Cont…
• Taking the z-transform of xint [n] c[n] x[n]
and making use of
1 M 1
c[n] WMkn
M k 0
we arrive at
M 1
n 1 kn n
X int ( z ) c[n]x[n] z M
W x[ n ] z
n M n k 0
1 M 1
1 M 1
kn n k
x
M k 0 n
[ n ]WM z
X z W M
30 M k 0
Spectrum of the Down-Sampler
• Consider a factor-of-2 down-sampler with
an input x[n] whose spectrum is as shown
below
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Cont…
x[n] h(n) M y[n]
as indicated below
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Cont…
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Down-Sampler
• For the general case, the relation between the
DTFTs of the output and the input of a factor-
of-M down-sampler is given by
1 M 1
j j ( 2 k ) / M )
Y (e )
M
X ( e
k 0
• j is a sum of M uniformly shifted
Y (e )
and stretched versions of and scaled
j )
by a factor of 1/M X ( e
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Original and Downsampled Spectrum
• Aliasing is absent if and only if
X (e j ) 0 for / M
as shown below for M = 2
X (e j ) 0 for / 2
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Down-Sampler
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Down-Sampler
• The input and output spectra of a down-sampler
with M = 3 are shown below
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Fractional Sampling Rate Alteration
Cascade Equivalences
• A complex multirate system is formed by an
interconnection of the up-sampler, the
down-sampler, and the components of an
LTI digital filter
• In many applications these devices appear
in a cascade form
• An interchange of the positions of the
branches in a cascade often can lead to a
computationally efficient realization
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Cascade Equivalences
• To implement a fractional change in the
sampling rate we need to employ a cascade
of an up-sampler and a down-sampler
• Consider the two cascade connections
shown below
x[n ] M L y1 [ n ]
x[n ] L M y2 [ n]
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Cascade Equivalences
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Cascade Equivalences
• Two other cascade equivalences are shown
below
Cascade equivalence #1
x[n ] M H (z ) y1 [ n ]
x[n ] H (z M ) M y1 [ n ]
Cascade equivalence #2
x[n ] L H (z L ) y2 [ n]
x[n ] H (z ) L y2 [ n]
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Filters in Sampling Rate Alteration
Systems
• From the sampling theorem it is known that a
the sampling rate of a critically sampled
discrete-time signal with a spectrum
occupying the full Nyquist range cannot be
reduced any further since such a reduction will
introduce aliasing
• Hence, the bandwidth of a critically sampled
signal must be reduced by lowpass filtering
before its sampling rate is reduced by a down-
sampler
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Signal Flow Graph
A collection of nodes and directed edges
– Node: computation or task
– Directed edge (j,k)
• a linear transformation from node j to node k
• Usually as constant gain multiplier or delay elements
– Widely used in digital filter structures
Basic blocks :
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Block Diagram
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Filters in Sampling Rate Alteration
Systems
• Likewise, the zero-valued samples introduced
by an up-sampler must be interpolated to
more appropriate values for an effective
sampling rate increase
• We shall show next that this interpolation can
be achieved simply by digital lowpass
filtering
• We now develop the frequency response
specifications of these lowpass filters
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Filter Specifications
• Since up-sampling causes periodic
repetition of the basic spectrum, the
unwanted images in the spectra of the up-
sampled signal xu [n] must be removed by
using a lowpass filter H(z), called the
interpolation filter,
filter as indicated below
xu [n]
x[n ] L H (z) y[n ]
frequency
Fs is the original sampling s
f p Fs / 2M
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Filter Specifications
Overall filter requirement for interpolation, to
avoid aliasing after rate reduction are
Passband 0 f f p
Stopband Fs / 2 M f Fs / 2
Passband deviation p
Stopband deviation s
Where
f p Fs / 2
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Filter Specifications
• On the other hand, prior to down-sampling,
the signal v[n] should be bandlimited to
/M by means of a
lowpass filter, called the decimation filter,
filter
as indicated below to avoid aliasing caused
by down-sampling
x[n ] H (z) M y[n ]
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Interpolation Filter Specifications
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Interpolation Filter Specifications
j 1, c / M
H (e )
0, / M
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Filter Design Methods
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Filters for Fractional Sampling
Rate Alteration
• A fractional change in the sampling rate can
be achieved by cascading a factor-of-M
decimator with a factor-of-L interpolator,
where M and L are positive integers
• Such a cascade is equivalent to a decimator
with a decimation factor of M/L or an
interpolator with an interpolation factor of
L/M
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Filters for Fractional Sampling
Rate Alteration
• There are two possible such cascade
connections as indicated below
H d (z) M L H u (z)
L H u (z) H d (z) M
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Computational Requirements
• This issue is not quite the same in the case
of multirate digital signal processing
• To illustrate this point further, consider the
factor-of-M decimator shown below
v[n ] y[n ]
x[n ] H (z) M
• If the decimation filter H(z) is an FIR filter
of length N implemented in a direct form,
then N 1
v[n] h[m] x[n m]
64 m 0
Computational Requirements
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1) Analysis Filter Bank
• It consist of M-sub filter.
• The individual Hk(z) is known as analysis filter.
• All the sub filter are equally spaced in frequancy
and each have the same frequancy.
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2) Synthesis Filter Bank
• It is dual of M-channel analysis bank K.
• Each Um(z) is fed to upsampler.
• The upsampling process produced the signal
Um(zm)
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3) Sub-Band Coding Filter Bank
• It is obtained by combining analysis and synthesis filter bank.
• Analysis filter bank splits the broadband input signal x(n).
• Synthesis filter bank is used to reconstruct output signal x(n)
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4) Quadrature Mirror Filter Bank
• It is a two channel sub-band coding filter bank with complementary
frequency response.
• It consist of two sections
• 1) Analysis section ,
Ho(z) –lowpass filter , H1(z) –highpass filter
• 2) Synthesis Section
Go(z) –lowpass filter , G1(z) –highpass filter
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Application of Multirate DSP
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DSP Processor
TMS320C54x
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Texas Instruments TMS320 Family Multiple DSP P
Generations
First Bit Size Clock Instruction MAC MOPS Device density (#
Sample speed Throughput execution of transistors)
(MHz) (ns)
Uniprocessor
Based
(Harvard
Architecture)
TMS32010 1982 16 integer 20 5 MIPS 400 5 58,000 (3)
Multiprocessor
Based
TMS320C80 1996 32 integer/flt. 2 GOPS MIMD
120 MFLOP
TMS320C62XX 1997 16 integer 1600 MIPS 5 20 GOPS VLIW
TMS310C67XX 1997 32 flt. pt. 5 1 GFLOP VLIW
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Features of TMS320C54x
Features provided by the ’54x DSPs include:
•High-performance, low-power ’C54x CPU
• Advanced multibus architecture with three separate 16-bit
data memory buses and one program memory bus
• 40-bit arithmetic logic unit (ALU), including a 40-bit barrel
shifter and two independent 40-bit accumulators
•17- × 17-bit parallel multiplier coupled to a 40-bit dedicated
adder for nonpipelined single-cycle multiply/accumulate
(MAC) operation
• Compare, select, and store unit (CSSU) for the add/compare
selection of the Viterbi operator
• Exponent encoder to compute an exponent value of a 40-bit
accumulator value in a single cycle
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Cont…
•Two address generators with eight auxiliary registers and two
auxiliary register arithmetic units (ARAUs)
• Data buses with a bus holder feature
• Extended addressing mode for up to 8M × 16-bit maximum
addressable external program space
• Single-instruction repeat and block-repeat operations for program
Code
•Block-memory-move instructions for better program and data
management
• Instructions with a 32-bit-long word operand
• Instructions with two- or three-operand reads
• Arithmetic instructions with parallel store and parallel load
• Conditional store instructions
• Fast return from interrupt
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On-chip peripherals :
•Software-programmable wait-state generator and programmable
bank-switching
• Phase-locked loop (PLL) clock generator with internal crystal
oscillator or external clock source
• Full-duplex standard serial port
•Time-division multiplexed (TDM) serial port
• Buffered serial port (BSP)
• Multichannel buffered serial port (McBSP)
• Direct memory access (DMA) controller
• 8-bit parallel host-port interface (HPI)
• Enhanced 8-bit parallel host-port interface (HPI8)
• 16-bit parallel host-port interface (HPI16)
• 16-bit timer with 4-bit prescaler
• Interprocessor first-in first-out (FIFO) unit (on multiple CPU
80 devices)
Architecture
The ’54x DSPs use an advanced, modified Harvard
architecture that maximizes processing power by
maintaining one program memory bus and three data
memory buses. These processors also provide an
arithmetic logic unit (ALU) that has a high degree of
parallelism, application-specific hardware logic, on-chip
memory, and additional on-chip peripherals. These DSP
families also provide a highly specialized instruction set,
which is the basis of the operational flexibility and speed
of these DSPs.
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Cont….
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Central Processing Unit (CPU)
The CPU of the ’54x devices contains:
A 40-bit arithmetic logic unit (ALU)
Two 40-bit accumulators
A barrel shifter
A 17 × 17-bit multiplier/adder
A compare, select, and store unit (CSSU)
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Accumulators
The accumulators, ACCA and ACCB, store the output from the
ALU or the multiplier / adder block; the accumulators can also
provide a second input to the ALU or the multiplier / adder. The
bits in each accumulator is grouped as follows:
• Guard bits (bits 32–39)
• A high-order word (bits 16–31)
• A low-order word (bits 0–15)
Instructions are provided for storing the guard bits, the high-order
and the low-order accumulator words in data memory, and for
manipulating 32-bit accumulator words in or out of data memory.
Also, any of the accumulators can be used as temporary storage
for the other.
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Barrel Shifter
The ’54x’s barrel shifter has a 40-bit input connected to the
accumulator or data memory (CB, DB) and a 40-bit output connected
to the ALU or data memory (EB). The barrel shifter produces a left
shift of 0 to 31 bits and a right shift of 0 to 16 bits on the input data.
Multiplier/Adder
The multiplier / adder performs 17 × 17-bit 2s-complement multiplication with a
40-bit accumulation in a single instruction cycle. The multiplier / adder block
consists of several elements: a multiplier, adder, signed/unsigned input control,
fractional control, a zero detector, a rounder (2s-complement),
overflow/saturation logic, and TREG. The multiplier has two inputs: one input is
selected from the TREG, a data-memory operand, or an accumulator; the other is
selected from the program memory, the data memory, an accumulator, or an
immediate value. The fast on-chip multiplier allows the ’54x to perform
operations such as convolution, correlation, and filtering efficiently.
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Compare, Select, and Store Unit (CSSU)
The compare, select, and store unit (CSSU) performs maximum
comparisons between the accumulator’s high and low words,
allows the test/control (TC) flag bit of status register 0 (ST0)
and the transition (TRN) register to keep their transition
histories, and selects the larger word in the accumulator to be
stored in data memory. The CSSU also accelerates Viterbi-type
butterfly computation with optimized on-chip hardware.
Program Control
Program control is provided by several hardware and software
mechanisms:
•Some of the hardware elements included in the program
controller are the program counter, the status and control
register, the stack, and the address-generation logic.
•Some of the software mechanisms used for program control
include branches, calls, conditional instructions, a repeat
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instruction, reset, and interrupts.
Status Registers (ST0, ST1)
The status registers, ST0 and ST1, contain the status of the various
conditions and modes for the ’54x devices. ST0 contains the flags
(OV, C, and TC) produced by arithmetic operations and bit
manipulations in addition to the data page pointer (DP) and the
auxiliary register pointer (ARP) fields. ST1 contains the various
modes and instructions that the processor operates on and
executes.
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Stack-Pointer Register (SP)
The SP is a 16-bit register that contains the address at the top of
the system stack. The SP always points to the last element pushed
onto the stack. The stack is manipulated by interrupts, traps, calls,
returns, and the PUSHD, PSHM, POPD, and POPM instructions.
Pushes and pops of the stack predecrement and postincrement,
respectively, all 16 bits of the SP.
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Block-Repeat Registers (BRC, RSA, REA)
The block-repeat counter (BRC) is a 16-bit register used to
specify the number of times a block of code is to be repeated
when performing a block repeat. The block-repeat start address
(RSA) is a 16-bit register containing the starting address of the
block of program memory to be repeated when operating in the
repeat mode. The 16-bit block-repeat end address (REA)
contains the ending address if the block of program memory is
to be repeated when operating in the repeat mode.
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Processor-Mode Status Register (PMST)
The processor-mode status register (PMST) controls memory
configurations of the ’54x devices.
Power-Down Modes
There are three power-down modes, activated by the IDLE1,
IDLE2, and IDLE3 instructions. In these modes, the ’54x devices
enter a dormant state and dissipate considerably less power than in
normal operation.
The IDLE1 instruction is used to shut down the CPU.
The IDLE2 instruction is used to shut down the CPU and on-chip
peripherals.
The IDLE3 instruction is used to shut down the ’54x processor
completely. This instruction stops the PLL circuitry as well as the
CPU and peripherals.
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Thank You
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