Lecture 03 Sequential Logic

Sequential Logic
Building a Modern Computer From First Principles
www.nand2tetris.org
Elements of Computing Systems, Nisan & Schocken, MIT Press, www.nand2tetris.org , Chapter 3: Sequential Logic slide 1
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Copyright © Noam Nisan and Shimon Schocken
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Sequential VS combinational logic
 Combinational devices: operate on data only;
provide calculation services (e.g. Nand … ALU)
 Sequential devices: operate on data and a clock signal;

as such, can be made to be state-aware and provide storage and
synchronization services
 Sequential devices are sometimes called “clocked devices”
 The low-level behavior of clocked / sequential gates is tricky
 The good news:
 All sequential chips can be based on one low-level sequential gate,

called “data flip flop”, or DFF
 The clock-dependency details can be encapsulated at the low-level DFF

level
 Higher-level sequential chips can be built on top of DFF gates using

combinational logic only.
Lecture plan
 Clock
 A hierarchy of memory chips:
 Flip-flop gates
 Binary cells
 Registers
 RAM
 Counters
 Perspective.
The Clock HW
simulator
demo
 In our jargon, a clock cycle = tick-phase (low), followed by a

tock-phase (high)
 In real hardware, the clock is implemented by an oscillator
 In our hardware simulator, clock cycles can be simulated either
 Manually, by the user, or
 “Automatically,” by a test script.

Flip-flop HW
simulator
demo
in DFF out
out(t) = in(t-1)
 A fundamental state-keeping device

 For now, let us not worry about the DFF implementation
 Memory devices are made from numerous flip-flops,
all regulated by the same master clock signal
 Notational convention:
1-bit register (we call it “Bit”)
Objective: build a storage unit that can:

(a) Change its state to a given input
(b) Maintain its state over time (until changed)
in out
DFF
out(t) = out(t-1) ?
out(t) = in(t-1) ?
Won’t work
Bit register (cont.) HW
simulator
demo
Interface Implementation
o Load bit
o Read logic
o Write logic
Multi-bit register HW
simulator
demo
o Register’s width: a trivial parameter

o Read logic
o Write logic
Aside: Hardware Simulation HW
simulator
demo
Relevant topics from the HW simulator tutorial:
 Clocked chips: When a clocked chip is loaded into the simulator, the
clock icon is enabled, allowing clock control
 Built-in chips:
 feature a standard HDL interface yet a Java implementation
 Provide behavioral simulation services
 May feature GUI effects (at the simulator level only).
Random Access Memory (RAM) HW
simulator
demo
o Read logic
o Write logic.
RAM interface
RAM anatomy
Recursive ascent
Counter
Needed: a storage device that can:
(a) set its state to some base value
(b) increment the state in every clock cycle
(c) maintain its state (stop incrementing) over clock cycles
(d) reset its state
If reset(t-1) then out(t)=0

else if load(t-1) then out(t)=in(t-1)
else if inc(t-1) then out(t)=out(t-1)+1
else out(t)=out(t-1)
 Typical function: program counter

 Implementation: register chip + some combinational logic.
Recap: Sequential VS combinational logic
Time matters
 During a tick-tock cycle, the internal states of all the clocked chips are allowed
to change, but their outputs are “latched”
 At the beginning of the next cycle, the outputs of all the clocked chips in the
architecture commit to the new values.
Implications:
 Challenge: propagation delays
 Solution: clock synchronization
 Cycle length and processing speed.
Perspective
 All the memory units described in this lecture are standard
 Typical memory hierarchy Access

time Cost
 SRAM (“static”), typically used for the cache
 DRAM (“dynamic”), typically used for main memory
 Disk
(Elaborate caching / paging algorithms)
 A Flip-flop can be built from Nand gates
 But ... real memory units are highly optimized, using a great variety of storage
technologies.
End notes: some poetry about the limits of logic ...
There exists a field where things are neither true nor false;
I’ll meet you there. (Rumi)
In the place where we are always right

No flowers will bloom in springtime (Yehuda Amichai)
A mind all logic is like a knife all blade;

It makes the hand bleed that uses it.
(Rabindranath Tagor)

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Sequential Logic

Building a Modern Computer From First Principles

Copyright © Noam Nisan and Shimon Schocken

We provide both PPT and PDF versions.

If you use our materials, please include a reference to www.nand2tetris.org

 Sequential devices: operate on data and a clock signal;

 Sequential devices are sometimes called “clocked devices”

 The low-level behavior of clocked / sequential gates is tricky

 The good news:

 All sequential chips can be based on one low-level sequential gate,

 The clock-dependency details can be encapsulated at the low-level DFF

 Higher-level sequential chips can be built on top of DFF gates using

 A hierarchy of memory chips:

 In our jargon, a clock cycle = tick-phase (low), followed by a

 In real hardware, the clock is implemented by an oscillator

 In our hardware simulator, clock cycles can be simulated either

 Manually, by the user, or

 “Automatically,” by a test script.

 A fundamental state-keeping device

Objective: build a storage unit that can:

o Register’s width: a trivial parameter

If reset(t-1) then out(t)=0

 Typical function: program counter

 Challenge: propagation delays

 Solution: clock synchronization

 Cycle length and processing speed.

 All the memory units described in this lecture are standard

 Typical memory hierarchy Access

 DRAM (“dynamic”), typically used for main memory

(Elaborate caching / paging algorithms)

 A Flip-flop can be built from Nand gates

In the place where we are always right

A mind all logic is like a knife all blade;

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