UNIT4

CMOS COMBINATIONAL AND SEQUENTIAL LOGIC CIRCUIT

DESIGN: Static CMOS Design: Complementary CMOS, Rationed
Logic, Pass-Transistor Logic. Dynamic CMOS Design: Dynamic Logic-
Basic Principles, Speed and Power Dissipation of Dynamic Logic,
Issues in Dynamic Design, Cascading Dynamic Gates, Choosing a
Logic Style, Gate Design in the Ultra Deep-Submicron Era, Latch
Versus Register, Latch based design, timing decimation, positive
feedback, in stability, Meta stability, multiplexer based latches,
Master-Slave Based Edge Triggered Register, clock to q delay, setup
time, hold time, reduced clock load master slave registers, Clocked
CMOS register. Cross coupled NAND and NOR, SR Master Slave
register, Storage mechanism, pipelining.
Even m1 is off
bcoz of reverse
biasing some
charge will
flow so it
causes charge
leakage
1A1 is changing from 0 to 1 and b=0 the asscociated parasitic capacitance of cm1 and cl
shares charge
As device operate in evalution mode mp share charge and clock also
share charge to the parasitic capacitance and ten occurs spikes in
clock is known as CF
In the waveforms when clk=1 imeediately ouput doesnot change from high to low so same
logic will be applied to the next stae so it causes malfunictioning of the logic in order to avoid
this problem domino logic preferred.