Chapter Seven

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Memory Management

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 Goals of memory management
Allocate memory resources among competing processes,
 maximizing memory utilization and system throughput
Provide isolation between processes
 No process shall overwrite other process’s location
Provide a convenient abstraction for programming (and
for compilers, etc.)

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 Tools of memory management
Base and limit registers
Swapping
Paging (and page tables and TLB’s)
Segmentation (and segment tables)
Page faults => page fault handling => virtual memory
The policies that govern the use of these mechanisms

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 Today’s desktop and server systems
The basic abstraction that the OS provides for memory
management is virtual memory (VM)
 Efficient use of hardware (real memory)
 VM enables programs to execute without requiring their entire
address space to be resident in physical memory
 Many programs don’t need all of their code or data at once (or
ever – branches they never take, or data they never read/write)
 No need to allocate memory for it, OS should adjust amount
allocated based on run-time behavior
 Program flexibility
 Programs can execute on machines with less RAM than they
“need”
 On the other hand, paging is really slow, so must be minimized!
 Protection
 Virtual memory isolates address spaces from each other
 One process cannot name addresses visible to others; each
process has its own isolated address space

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 VM requires hardware and OS support
MMU’s, TLB’s, page tables, page fault handling, …
Typically accompanied by swapping, and at least limited
segmentation

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 A trip down Memory Lane …
Single task system
Why?
 Because it’s instructive
 Because embedded processors (98% or more of all processors)
typically don’t have virtual memory
 An embedded system may have only one program!

 Because some aspects are pertinent to allocating portions of a virtual

address space – e.g., malloc()

First, there was job-at-a-time batch programming

 Programs used physical addresses directly
 OS loads job (perhaps using a relocating loader to “offset” branch
addresses), runs it, unloads it
 What if the program wouldn’t fit into memory?
 manual overlays!

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 Cont…
Swapping
 save a program’s entire state (including its memory image) to disk
 allows another program to be run
 first program can be swapped back in and re-started right where it
was

The first timesharing system, MIT’s “Compatible Time

Sharing System” (CTSS), was a uni-programmed swapping
system
 only one memory-resident user
 upon request completion or quantum expiration, a swap took place

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Then came multiprogramming
 multiple processes/jobs in memory at once
 to overlap I/O and computation between processes/jobs,
easing the task of the application programmer
 memory management requirements:
 protection: restrict which addresses processes can use, so
they can’t stomp on each other
 fast translation: memory lookups must be fast, in spite of
the protection scheme
 fast context switching: when switching between jobs,
updating memory hardware (protection and translation) must
be quick

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 Logical vs. Physical Address Space
Logical address – is address generated by the CPU;
 also referred to as virtual address
Physical address – address seen by the memory unit

Logical address space is the set of all logical addresses

generated by a program
Physical address space is the set of all physical
addresses generated by a program

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 Memory-Management Unit (MMU)
Hardware device that at run time maps virtual to physical
address

Many methods possible, covered in the rest of this chapter

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 Memory-Management Unit (Cont.)
Consider simple scheme. which is a generalization of the
base-register scheme.
 The base register now called relocation register
The value in the relocation register is added to every
address generated by a user process at the time it is sent
to memory

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 Contiguous Allocation
Contiguous allocation is one early method
In contiguous allocation, each process contained in single
contiguous section of memory
Main memory must support both OS and user processes
Hence, Main memory usually splits into two partitions:
 Resident operating system, usually held in low memory with
interrupt vector
 User processes then held in high memory

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 Contiguous Allocation (Cont.)
Relocation registers used to protect user processes from
each other, and from changing operating-system code and
data
 Base register contains value of smallest physical address
 Limit register contains range of logical addresses – each logical
address must be less than the limit register
 MMU maps logical address dynamically

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Contiguous Allocation technique #1: Fixed partitions
Physical memory is broken up into fixed partitions
 partitions may have different sizes, but partitioning never changes
 hardware requirement: base register, limit register
 physical address = virtual address + base register
 base register loaded by OS when it switches to a process
 how do we provide protection?
 if (physical address > base + limit) then… ?

Advantages
 Simple
Problems
 internal fragmentation: the available partition is larger than what
was requested
 external fragmentation: two small partitions left, but one big job –
what sizes should the partitions be??

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 Mechanics of fixed partitions

physical memory

0
limit register base register partition 0
2K
2K P2’s base: 6K
partition 1

6K
yes
offset <? + partition 2
virtual address 8K
no
partition 3
raise
protection fault
12K

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Contiguous Allocation technique #2: Variable partitions
Obvious next step: physical memory is broken up into
partitions dynamically – partitions are tailored to programs
 hardware requirements: base register, limit register
 physical address = virtual address + base register
 how do we provide protection?
 if (physical address > base + limit) then… ?

Advantages
 no internal fragmentation
 simply allocate partition size to be just big enough for process
(assuming we know what that is!)
Problems
 external fragmentation
 as we load and unload jobs, holes are left scattered throughout
physical memory

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 Mechanics of variable partitions

physical memory

limit register base register partition 0

P3’s size P3’s base
partition 1

partition 2
yes
offset <? + partition 3
virtual
address no

raise
protection fault partition 4

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 Dealing with fragmentation

Compaction:- Compact
memory by copying
 Swap a program out partition 0 partition 0
 Re-load it, adjacent
partition 1 partition 1
to another
partition 2
 Adjust its base partition 2 partition 3
register
partition 3 partition 4
 “Lather, rinse,
repeat”
Very expensive partition 4

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 Memory Management Problems
Fixed partitions
 Suffer from internal fragmentation
Variable partitions
 Suffer from external fragmentation
Compaction
 Suffer from overhead
Swapping
 Requires writing to disk sectors

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 Modern techniques

• Segmentation
• Paging

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 Segmentation
Segmentation is non-contiguous memory allocation technique.
It is Memory-management scheme that supports user view of memory
A program is a collection of segments
 A segment is a logical unit such as:
main program
procedure
function
method
object
local variables, global variables
common block
stack
symbol table
arrays

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User’s View of a Program

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 Logical View of Segmentation

1
4
1
2

3 2
4
3

user space physical memory space

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 Characteristics
 
Segmentation is a variable size partitioning scheme.
 memory divided into partitions of unequal size.
The size of partitions depend on the length of modules.
The partitions of secondary memory are called
as segments.

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 Segmentation Architecture
Logical address consists of a two parts:
<segment-number, offset>,
Segment table – It maps two-dimensional Logical address
into one-dimensional Physical address. 
 each table entry has:
 base – contains the starting physical address where the
segments reside in memory
 limit – specifies the length of the segment

Segment-table base register (STBR) points to the

segment table’s location in memory
Segment-table length register (STLR) indicates number
of segments used by a program;
segment number s is legal if s < STLR
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 Segmentation Architecture (Cont.)
Protection
 With each entry in segment table associate:
 validation bit = 0  illegal segment
 read/write/execute privileges

Protection bits associated with segments; code sharing

occurs at segment level

Since segments vary in length, memory allocation is a

dynamic storage-allocation problem
A segmentation example is shown in the following diagram

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Segmentation Hardware

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 Example

Segmentation with Paging

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 Paging
It is another noncontiguous memory allocation scheme
Divide physical memory into fixed-sized blocks called frames
 Size is power of 2, between 512 bytes and 16 Mbytes
Divide logical memory into blocks of same size called pages
Keep track of all free frames
To run a program of size N pages, need to find N free frames and load
program
Uses a page table to translate logical to physical addresses
Backing store likewise split into pages
Still have Internal fragmentation
Process is allocated physical memory whenever the latter is available
 Avoids external fragmentation which is the problem of varying sized
memory chunks

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 Address Translation Scheme
 Address generated by CPU is divided into:
 Page number (p) – used as an index into a page table which
contains base address of each page in physical memory
 Page offset (d) – combined with base address to define the
physical memory address that is sent to the memory unit

page number page offset

p d
m -n n

 For given logical address space 2m and page size 2n

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Paging Hardware

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Paging Model of Logical and Physical Memory

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 Formula on address transliteration
For Process
 Virtual Address Space = Size of process
 Number of pages the process is divided = Process size / Page size
 If process size = 2X bytes, then number of bits in virtual address space = X bits
For Page Table-
 Size of page table = Number of entries in page table x Page table entry size
 Number of entries in pages table = Number of pages the process is divided
 Page table entry size = Number of bits in frame number + Number of bits used
for optional fields if any
For Main Memory-
 Physical Address Space = Size of main memory
 Size of main memory = Total number of frames x Page size
 Frame size = Page size
 If number of frames in main memory = 2n, then number of bits in frame number = n bits
 If Page size = 2n Bytes, then number of bits in page offset = n bits
 If size of main memory = 2n Bytes, then number of bits in physical address = n bits
 If the memory is byte-addressable, then size of one location = 1 byte.
 If the memory is word-addressable where 1 word = m bytes, then size of one location =
m bytes.
 Thus, size of memory = 2n x m bytes.
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 Paging Example

4-byte pages i.e n=2 and

16-byte logical address space i.e m=4
32-byte memory
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 Example
1) Calculate the size of memory if its address consists of 22
bits and the memory is 2-byte addressable.
Solution
 Number of locations possible with 22 bits = 222 locations
 It is given that the size of one location = 2 bytes 
 Thus, Size of memory = 222 x 2 bytes = 223 bytes = 8 MB
2) Consider a system with byte-addressable memory, 32 bit
logical addresses, 4 kilobyte page size and page table entries
of 4 bytes each. What is the size of the page table ?
Solution
 Number of pages the process is divided
 = Process size / Page size => 232 / 212
 = 220 pages (entries)

 Number of entries in page table x Page table entry size

 = 220 x 4 bytes = 4 MB
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 Cont…
Consider a system with a 6 bit virtual address space, and 16 byte
pages/frames. The mapping from virtual page numbers to physical
frame numbers of a process is (0,8), (1,3), (2,11), and (3,1). Translate
virtual addresses 20 to a physical addresses. Note that addresses is in
decimal. You may write your answer in decimal or binary.
a) 20
Solution:
 Page number = 26/24= 2bits for page number && 4bits offset
 Convert 20 into binary = 20 = 01 0100 (page1)
 Consult the page table = page 1 is in frame 3 (binary 11)
 Concatenate frame number with offset = 11 0100
 Therefore the physical address is 11 0100 (or decimal 52)
OR
 P= 20/16= 1.***(ignore the decimals, page number is 1)
 d(offset)=20%16= 4
 Consult page table= page1 is in frame 3
 The base address 3*16 = 48
 Actual address is base + d = 48+4 = 52
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 Paging (Cont.)
Calculating internal fragmentation
 Page size = 2,048 bytes
 Process size = 72,766 bytes
 35 pages + 1,086 bytes
 Internal fragmentation of 2,048 - 1,086 = 962 bytes
 Worst case fragmentation = 1 frame – 1 byte
 On average fragmentation = 1 / 2 frame size
 So small frame sizes desirable?
 But each page table entry takes memory to track

 Page sizes growing over time

 Solaris supports two page sizes – 8 KB and 4 MB

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 Free Frames

Before allocation After allocation

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 Implementation of Page Table
Page table is kept in main memory
Page-table base register (PTBR) points to the page table
Page-table length register (PTLR) indicates size of the
page table
In this scheme every data/instruction access requires two
memory accesses
 One for the page table and one for the data / instruction
The two memory access problem can be solved by the use
of a special fast-lookup hardware cache called associative
memory or translation look-aside buffers (TLBs)

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 Implementation of Page Table (Cont.)
Some TLBs store address-space identifiers (ASIDs) in
each TLB entry – uniquely identifies each process to
provide address-space protection for that process
 Otherwise need to flush at every context switch
TLBs typically small (64 to 1,024 entries)
On a TLB miss, value is loaded into the TLB for faster
access next time
 Replacement policies must be considered
 Some entries can be wired down for permanent fast access

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 Associative Memory
Associative memory – parallel search

P a ge # F ra m e #

Address translation (p, d)

 If p is in associative register, get frame # out
 Otherwise get frame # from page table in memory

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Paging Hardware With TLB

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 Effective Access Time
 Hit ratio – percentage of times that a page number is found in the TLB
 An 80% hit ratio means that we find the desired page number in the
TLB 80% of the time.
 Suppose that 10 nanoseconds to access memory.
 If we find the desired page in TLB then a mapped-memory access
take 10 ns
 Otherwise we need two memory access so it is 20 ns
 Effective Access Time (EAT)
EAT = 0.80 x 10 + 0.20 x 20 = 12 nanoseconds
implying 20% slowdown in access time
 Consider amore realistic hit ratio of 99%,
EAT = 0.99 x 10 + 0.01 x 20 = 10.1ns
implying only 1% slowdown in access time.

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 Memory Protection
Memory protection implemented by associating protection
bit with each frame to indicate if read-only or read-write
access is allowed
 Can also add more bits to indicate page execute-only, and so on
Valid-invalid bit attached to each entry in the page table:
 “valid” indicates that the associated page is in the process’ logical
address space, and is thus a legal page
 “invalid” indicates that the page is not in the process’ logical
address space
 Or use page-table length register (PTLR)
Any violations result in a trap to the kernel

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Valid (v) or Invalid (i) Bit In A Page Table

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 Shared Pages
Shared code
 One copy of read-only (reentrant) (non self modifying code) shared
among processes (i.e., text editors, compilers, window systems)
 reentrant code never changes during execution.
 Thus, two or more processes can execute the same code at the same
time.
 Similar to multiple threads sharing the same process space
 Also useful for inter-process communication if sharing of read-write
pages is allowed
 Shared code(Pages) must appear in same location in the logical
address space of all processes.
Private code and data
 Each process keeps a separate copy of the code and data
 The pages for the private code and data can appear anywhere in
the logical address space

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Shared Pages Example

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 Structure of the Page Table
Memory structures for paging can get huge using straight-
forward methods
 Consider a 32-bit logical address space as on modern computers
 Page size of 4 KB (212)
 Page table would have 1 million entries (232 / 212)
 If each entry is 4 bytes -> 4 MB of physical address space /
memory for page table alone
 That amount of memory used to cost a lot
 Don’t want to allocate that contiguously in main memory

Solution
 Hierarchical Paging
 Hashed Page Tables
 Inverted Page Tables

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 Hierarchical Page Tables
Break up the logical address space into multiple page
tables
A simple technique is a two-level page table
We then page the page table

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Two-Level Page-Table Scheme

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 Two-Level Paging Example
A logical address (on 32-bit machine with 1K page size) is
divided into:
 a page number consisting of 22 bits
 a page offset consisting of 10 bits

Since the page table is paged, the page number is further

divided into:
 a 12-bit page number
 a 10-bit page offset

Thus, a logical address is as follows:

where p1 is an index into the outer page table, and p2 is the

displacement within the page of the inner page table
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Address-Translation Scheme

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 64-bit Logical Address Space
 Even two-level paging scheme not sufficient
 If page size is 4 KB (212)
 Then page table has 252 entries
 If two level scheme, inner page tables could be 210 4-byte entries
 Address would look like

 Outer page table has 242 entries or 244 bytes

 One solution is to add a 2nd outer page table
 But in the following example the 2nd outer page table is still 234 bytes
in size
 And possibly 4 memory access to get to one physical memory
location
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Three-level Paging Scheme

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 Hashed Page Tables
Common in address spaces > 32 bits
The virtual page number is hashed into a page table
 This page table contains a chain of elements hashing to the same
location
Each element contains (1) the virtual page number (2) the
value of the mapped page frame (3) a pointer to the next
element
Virtual page numbers are compared in this chain searching
for a match
 If a match is found, the corresponding physical frame is extracted

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Hashed Page Table

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 Inverted Page Table
Rather than each process having a page table and keeping track of all
possible logical pages, track all physical pages
There is only a single table
 One entry for each real page of memory
 Entry consists of
 Virtual address of the page stored in that real memory location, and
 PID of the process that owns that page
Advantage
 Decreases memory needed to store each page table,
Disadvantage
 increases time needed to search the table when a page reference occurs
 However, TLB can accelerate access

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Inverted Page Table Architecture

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End of Chapter Seven

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