COMI Unit2

MIT Art Design & Technology University’s
MIT School of Engineering, Pune
COMPUTER ORGANIZATION &

MICROPROCESSORS INTERFACING
UNIT II : INTRODUCTION TO
MICROPROCESSORS AND
PROCESSOR ORGANIZATION
8086 Features
2
 16-bit processor
 16-bit data bus and 20-bit address bus
 20-bit memory address and 16-bit I/O address
 Provides fourteen 16-bit registers
 Multiplexed lines
 Perform bit, byte, word and block transfer
 Operate in min and max mode
 Multiprogramming
 Fetch up-to six instruction bytes from memory and stores it in queue
 Supports different addressing modes
Block Diagram of 8086
3
Memory Organization of 8086
4
Instruction Queue
5
Instruction Pointer
6
Common signals
Pins and Signals

7
AD0-AD15 (Bidirectional)
Address/Data bus
Low order address bus; these are

multiplexed with data.
When AD lines are used to transmit

memory address the symbol A is used
instead of AD, for example A0-A15.
When data are transmitted over AD lines

the symbol D is used in place of AD, for
example D0-D7, D8-D15 or D0-D15.
A16/S3, A17/S4, A18/S5, A19/S6
High order address bus. These are

multiplexed with status signals
Common signals
Pins and Signals

8
BHE (Active Low)/S7 (Output)
Bus High Enable/Status
It is used to enable data onto the most

significant half of data bus, D8-D15. 8-bit
device connected to upper half of the
data bus use BHE (Active Low) signal. It
is multiplexed with status signal S7.
MN/ MX
MINIMUM / MAXIMUM
This pin signal indicates what mode the

processor is to operate in.
RD (Read) (Active Low)
The signal is used for read operation.

It is an output signal.
It is active when low.
Common signals
Pins and Signals

9
READY
This is the acknowledgement from the

slow device or memory that they have
completed the data transfer.
The signal is active high.

Common signals
Pins and Signals

10
RESET (Input)
Causes the processor to immediately

terminate its present activity.
The signal must be active HIGH for at
least four clock cycles.
CLK
The clock input provides the basic timing

for processor operation and bus control
activity. Its an asymmetric square wave
with 33% duty cycle.
INTR Interrupt Request
This is a triggered input. This is sampled

during the last clock cycles of each
instruction to determine the availability
of the request. If any interrupt request is
pending, the processor enters the
interrupt acknowledge cycle.
Min/ Max Pins
Pins and Signals
11
The 8086 microprocessor can work in two

modes of operations : Minimum mode and
Maximum mode.
In the minimum mode of operation the

microprocessor do not associate with any
co-processors and can not be used for
multiprocessor systems.
In the maximum mode the 8086 can work

in multi-processor or co-processor
configuration.
Minimum or maximum mode operations

are decided by the pin MN/ MX(Active
low).
When this pin is high 8086 operates in

minimum mode otherwise it operates in
Maximum mode.
Minimum mode signals
Pins and Signals

12
ALE (Address Latch Enable) Used to demultiplex the

address and data lines using external latches
Minimum mode signals
Pins and Signals

13
HOLD Input signal to the processor form the bus masters

as a request to grant the control of the bus.
Usually used by the DMA controller to get the

control of the bus.
HLDA (Hold Acknowledge) Acknowledge signal by the

processor to the bus master requesting the control
of the bus through HOLD.
The acknowledge is asserted high, when the

processor accepts HOLD.
Maximum mode signals
Pins and Signals

14
Pins and Signals

15
Pins and Signals

16
Architecture
17
Code Segment Register

Segment
Registers 16-bit
CS contains the base or start of the current code segment; IP contains the
distance or offset from this address to the next instruction byte to be fetched.
BIU computes the 20-bit physical address by logically shifting the contents of
CS 4-bits to the left and then adding the 16-bit contents of IP.
That is, all instructions of a program are relative to the contents of the CS
register multiplied by 16 and then offset is added provided by the IP.
Data Segment Register

16-bit
Points to the current data segment; operands for most instructions are fetched
from this segment.
The 16-bit contents of the Source Index (SI) or Destination Index (DI) or a 16-
bit displacement are used as offset for computing the 20-bit physical address.
Architecture
18
Segment Stack Segment Register

Registers
16-bit
Points to the current stack.
The 20-bit physical stack address is calculated from the Stack Segment (SS) and
the Stack Pointer (SP) for stack instructions such as PUSH and POP.
In based addressing mode, the 20-bit physical stack address is calculated from
the Stack segment (SS) and the Base Pointer (BP).
Extra Segment Register

16-bit
Points to the extra segment in which data (in excess of 64K pointed to by the
DS) is stored.
String instructions use the ES and DI to determine the 20-bit physical address
for the destination.
Architecture
19
Segment Instruction Pointer

Registers
16-bit
Always points to the next instruction to be executed within

the currently executing code segment.
So, this register contains the 16-bit offset address pointing

to the next instruction code within the 64Kb of the code
segment area.
Its content is automatically incremented as the execution of

the next instruction takes place.
Instruction Queue
A group of First-In-First-Out (FIFO) in which up to 6 bytes of
instruction code are pre fetched from the memory ahead of time.
This is done in order to speed up the execution by overlapping

instruction fetch with execution.
This mechanism is known as pipelining.

Architecture
20
Accumulator Register (AX)

EU Consists of two 8-bit registers AL and AH, which can be combined
Registers together and used as a 16-bit register AX.
AL in this case contains the low order byte of the word, and AH
contains the high-order byte.
The I/O instructions use the AX or AL for inputting / outputting

16 or 8 bit data to or from an I/O port.
Multiplication and Division instructions also use the AX or AL.
Base Register (BX)
Consists of two 8-bit registers BL and BH, which can be combined

together and used as a 16-bit register BX.
BL in this case contains the low-order byte of the word, and BH

contains the high-order byte.
This is the only general purpose register whose contents can be

used for addressing the 8086 memory.
All memory references utilizing this register content for

addressing use DS as the default segment register.
Architecture
21
Counter Register (CX)

EU
Registers Consists of two 8-bit registers CL and CH, which can be combined
together and used as a 16-bit register CX.
When combined, CL register contains the low order byte of the

word, and CH contains the high-order byte.
Instructions such as SHIFT, ROTATE and LOOP use the contents

of CX as a counter.
Architecture
22
Stack Pointer (SP) and Base Pointer (BP)

EU
Registers SP and BP are used to access data in the stack segment.
SP is used as an offset from the current SS during execution

of instructions that involve the stack segment in the external
memory.
SP contents are automatically updated (incremented/

decremented) due to execution of a POP or PUSH instruction.
BP contains an offset address in the current SS, which is

used by instructions utilizing the based addressing mode.
Source Index (SI) and Destination Index (DI)
Used in indexed addressing.
Instructions that process data strings use the SI and DI

registers together with DS and ES respectively in order to
distinguish between the source and destination addresses.
Flag Register
Auxiliary Carry Flag
Carry Flag
This is set, if there is a carry from the
23 lowest nibble, i.e, bit three during This flag is set, when there is
addition, or borrow for the lowest a carry out of MSB in case of
nibble, i.e, bit three, during addition or a borrow in case
subtraction. of subtraction.
Sign Flag Zero Flag Parity Flag
This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation the computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1’s ; for odd number
zero of 1’s set to zero.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF DF IF TF SF ZF AF PF CF
Tarp Flag
Over flow Flag If this flag is set, the processor
This flag is set, if an overflow occurs, i.e, if the result of a signed
enters the single step execution
operation is large enough to accommodate in a destination
mode by generating internal
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit interrupts after the execution of
sign operations, then the overflow will be set. each instruction
Direction Flag Interrupt Flag

This is used by string manipulation instructions. If this flag bit
is ‘0’, the string is processed beginning from the lowest Causes the 8086 to recognize
address to the highest address, i.e., auto incrementing mode. external mask interrupts; clearing IF
Otherwise, the string is processed from the highest address disables these interrupts.
towards the lowest address, i.e., auto incrementing mode.
Addressing Modes
Every instruction of a program has to operate on a data.
24 The different ways in which a source operand is denoted
in an instruction are known as addressing modes.
1. Register Addressing
Group I : Addressing modes for
2. Immediate Addressing register and immediate data
3. Direct Addressing
4. Register Indirect Addressing
5. Based Addressing
Group II : Addressing modes for memory
6. Indexed Addressing data
7. Based Index Addressing
8. String Addressing
9. Direct I/O port Addressing

Group III : Addressing modes for I/O
10. Indirect I/O port Addressing ports
11. Relative Addressing Group IV : Relative Addressing mode
12. Implied Addressing Group V : Implied Addressing mode

register and immediate data
Addressing Modes
25
The instruction will specify the name of the

register which holds the data to be operated by
2. Immediate Addressing the instruction.
3. Direct Addressing Example:
4. Register Indirect Addressing MOV CL, DH
5. Based Addressing The content of 8-bit register DH is moved to

another 8-bit register CL
6. Indexed Addressing
(CL)  (DH)
10. Indirect I/O port Addressing
11. Relative Addressing
12. Implied Addressing

register and immediate data
Addressing Modes
26
1. Register Addressing In immediate addressing mode, an 8-bit or 16-bit

data is specified as part of the instruction
2. Immediate Addressing
Example:
4. Register Indirect Addressing MOV DL, 08H
5. Based Addressing The 8-bit data (08H) given in the instruction is

moved to DL
(DL)  08H
MOV AX, 0A9FH
The 16-bit data (0A9FH) given in the instruction is
10. Indirect I/O port Addressing moved to AX register
11. Relative Addressing (AX)  0A9FH

Group II : Addressing modes for
memory data
Addressing Modes
27
Here, the effective address of the memory

1. Register Addressing location at which the data operand is stored is
given in the instruction.
The effective address is just a 16-bit number
3. Direct Addressing written directly in the instruction.

Example:
5. Based Addressing
MOV BX, [1354H]
6. Indexed Addressing MOV BL, [0400H]

7. Based Index Addressing The square brackets around the 1354H denotes
the contents of the memory location. When
8. String Addressing executed, this instruction will copy the contents of
the memory location into BX register.
This addressing mode is called direct because the
10. Indirect I/O port Addressing displacement of the operand from the segment
base is specified directly in the instruction.

memory data
Addressing Modes
28
1. Register Addressing In Register indirect addressing, name of the

register which holds the effective address (EA)
2. Immediate Addressing will be specified in the instruction.
3. Direct Addressing Registers used to hold EA are any of the following

registers:
BX, BP, DI and SI.
5. Based Addressing
Content of the DS register is used for base
address calculation.
Example:
MOV CX, [BX]

Addressing Modes
memory data
29
In Based Addressing, BX or BP is used to hold the
1. Register Addressing base value for effective address and a signed 8-bit
or unsigned 16-bit displacement will be specified
2. Immediate Addressing in the instruction.
3. Direct Addressing In case of 8-bit displacement, it is sign extended

to 16-bit before adding to the base value.
When BX holds the base value of EA, 20-bit
5. Based Addressing physical address is calculated from BX and DS.
When BP holds the base value of EA, BP and SS is
used.
8. String Addressing Example:
9. Direct I/O port Addressing MOV AX, [BX + 08H]
10. Indirect I/O port Addressing Operations:
11. Relative Addressing 0008H  08H (Sign extended)

EA = (BX) + 0008H
12. Implied Addressing BA = (DS) x 1610
MA = BA + EA
Addressing Modes
memory data
30
1. Register Addressing SI or DI register is used to hold an index value for

memory data and a signed 8-bit or unsigned 16-
2. Immediate Addressing bit displacement will be specified in the
instruction.
Displacement is added to the index value in SI or
4. Register Indirect Addressing DI register to obtain the EA.
5. Based Addressing In case of 8-bit displacement, it is sign extended
to 16-bit before adding to the base value.

Example:
MOV CX, [SI + 0A2H]
Operations:
FFA2H  A2H (Sign extended)
EA = (SI) + FFA2H
12. Implied Addressing BA = (DS) x 1610
MA = BA + EA
memory data
Addressing Modes
31
In Based Index Addressing, the effective address
2. Immediate Addressing is computed from the sum of a base register (BX
or BP), an index register (SI or DI) and a
3. Direct Addressing displacement.
4. Register Indirect Addressing Example:
5. Based Addressing MOV DX, [BX + SI + 0AH]
6. Indexed Addressing Operations:

000AH  0AH (Sign extended)
EA = (BX) + (SI) + 000AH
9. Direct I/O port Addressing BA = (DS) x 1610
MA = BA + EA

memory data
Addressing Modes
32
1. Register Addressing Employed in string operations to operate on string

data.
The effective address (EA) of source data is stored
3. Direct Addressing in SI register and the EA of destination is stored
in DI register.
Segment register for calculating base address of
5. Based Addressing source data is DS and that of the destination data
is ES

Example: MOVS BYTE
Operations:
Calculation of source memory location:
10. Indirect I/O port Addressing EA = (SI) BA = (DS) x 1610 MA = BA + EA
11. Relative Addressing Calculation of destination memory location:

EAE = (DI) BAE = (ES) x 1610 MAE = BAE + EAE
Group III : Addressing modes
for I/O ports
Addressing Modes
33
These addressing modes are used to access data from
1. Register Addressing standard I/O mapped devices or ports.
2. Immediate Addressing In direct port addressing mode, an 8-bit port address

is directly specified in the instruction.
Example: IN AL, [09H]
Operations: PORTaddr = 09H
5. Based Addressing (AL)  (PORT)
6. Indexed Addressing Content of port with address 09H is

moved to AL register
In indirect port addressing mode, the instruction will
8. String Addressing specify the name of the register which holds the port
address. In 8086, the 16-bit port address is stored in
9. Direct I/O port Addressing the DX register.
10. Indirect I/O port Addressing Example: OUT [DX], AX
11. Relative Addressing Operations: PORTaddr = (DX)

(PORT)  (AX)
Content of AX is moved to port
whose address is specified by DX
Group IV : Relative
Addressing mode
Addressing Modes
34
1. Register Addressing In this addressing mode, the effective address of

a program instruction is specified relative to
2. Immediate Addressing Instruction Pointer (IP) by an 8-bit signed
displacement.
Example: JZ 0AH
5. Based Addressing Operations:
6. Indexed Addressing 000AH  0AH (sign extend)
7. Based Index Addressing EA = (IP) + 000AH

BA = (CS) x 1610
MA = BA + EA

Group IV : Implied
Addressing mode
Addressing Modes
35
4. Register Indirect Addressing Instructions using this mode have no operands.

The instruction itself will specify the data to be
5. Based Addressing operated by the instruction.
Example: CLC
This clears the carry flag to zero.

Interrupts
36
 Interrupt is the method of creating a temporary halt during program

execution and allows peripheral devices to access the
microprocessor. The microprocessor responds to that interrupt with
an ISR (Interrupt Service Routine), which is a short program to
instruct the microprocessor on how to handle the interrupt
8086 Interrupts
37
8086 Hardware Interrupts
38
 NMI
 It is a single non-maskable interrupt pin (NMI) having higher priority than
the maskable interrupt request pin (INTR)and it is of type 2 interrupt.
 When this interrupt is activated, these actions take place −
 Completes the current instruction that is in progress.
 Pushes the Flag register values on to the stack.
 Pushes the CS (code segment) value and IP (instruction pointer) value of
the return address on to the stack.
 IP is loaded from the contents of the word location 00008H.
 CS is loaded from the contents of the next word location 0000AH.
 Interrupt flag and trap flag are reset to 0.
8086 Hardware Interrupts
39
 INTR
 The INTR is a maskable interrupt because the microprocessor will be
interrupted only if interrupts are enabled using set interrupt flag
instruction. The INTR interrupt is activated by an I/O port.
 These actions are taken by the microprocessor −
 First completes the current instruction.
 Activates INTA output and receives the interrupt type, say X.
 Flag register value, CS value of the return address and IP value of the
return address are pushed on to the stack.
 IP value is loaded from the contents of word location X × 4
 CS is loaded from the contents of the next word location.
 Interrupt flag and trap flag is reset to 0
8086 Software Interrupts
40
 TYPE 0 interrupt represents division by zero situation.

 TYPE 1 interrupt represents single-step execution during the
debugging of a program.
 TYPE 2 interrupt represents non-maskable NMI interrupt.
 TYPE 3 interrupt represents break-point interrupt.
 TYPE 4 interrupt represents overflow interrupt.
 The interrupts from Type 5 to Type 31 are reserved for other
advanced microprocessors, and interrupts from 32 to Type
255 are available for hardware and software interrupts
Interrupt Vector Table
41
42
 The interrupt vector (or interrupt pointer) table is the link between an
interrupt type code and the procedure that has been designated to service
interrupts associated with that code. 8086 supports total 256 types i.e. 00H
to FFH.
 For each type it has to reserve four bytes i.e. double word. This double
word pointer contains the address of the procedure that is to service
interrupts of that type.
 The higher addressed word of the pointer contains the base address of the
segment containing the procedure. This base address of the segment is
normally referred as NEW CS.
 The lower addressed word contains the procedure’s offset from the
beginning of the segment. This offset is normally referred as NEW IP.
 Thus NEW CS: NEW IP provides NEW physical address from where user
ISR routine will start.
43
 As for each type, four bytes (2 for NEW CS and 2 for NEW IP) are
required; therefore interrupt pointer table occupies up to the first 1k bytes
(i.e. 256 x 4 = 1024 bytes) of low memory.
 The total interrupt vector table is divided into three groups namely,
 A. Dedicated interrupts (INT 0…..INT 4)
 B. Reserved interrupts (INT 5…..INT 31)
 C. Available interrupts (INT 32…..INT 225)
80386
44
80386 Features
45
Architecture
46
47
Bus Interfacing Unit
48
Code Prefetch Unit
49
Instruction Decode Unit
50
Segmentation Unit
51
Paging Unit
52
Execution Unit
53
Registers in 80386
54
 General purpose register

 Segment Register
 Index, pointers & base registers
 Flag register- 32 bit
IOPL- I/O privilege level- 0-3 level

NT- Nested Flag
RF- Resume Flag
VM- Virtual Memory- bit set
55
 System address register- holds the addresses for four special

descriptor table segment.
TR- Task register
IDTR- Interrupt descriptor table register
GDTR- Global descriptor table register
LDTR- Local descriptor table register
 Control register
CR0 –CR3 – control various features

 Debug register
DR0- DR7 – Facilitate debugging

Register Organization (1)
56
 Registers form the highest level of the memory

hierarchy
 Small set of high speed storage locations
 Temporary storage for data and control information
 Two types of registers
 User-visible
 May be referenced by assembly-level instructions and are
thus “visible” to the user
 Control and status registers
 Used to control the operation of the CPU
 Most are not visible to the user
57
 User Visible Registers

 General purpose
 Can be assigned a variety of functions
 Ideally, they are defined orthogonally to the operations
within the instructions
 Data
 These registers only hold data
 Address
 These registers only hold address information
 Examples: general purpose address registers, segment
registers, stack pointers, index registers
58
 User Visible Registers

 Condition codes
 Visible to the user but values set by the CPU as the result of
performing operations
 Example code bits: zero, positive, overflow
 Bit values are used as the basis for conditional jump
instructions
59
 Trade off between general purpose and specialized

registers
 General purpose registers maximize flexibility in
instruction design
 Special purpose registers permit implicit register
specification in instructions – reduces register field
size in an instruction.
60
 How many registers?

 More registers permit more operands to be held within
the CPU reducing memory bandwidth requirements to
some extent.
 More registers cause an increase in the field sizes
needed to specify registers in an instruction word.
 Locality of reference may not support too many
registers
 Most machines use 8-32 registers
61
 How big registers?

 Address registers should be wide enough to hold the
longest address.
 Data registers should be wide enough to hold most data
types
 Related to width of memory data bus.
 Control and status registers
 These registers are used during the fetching, decoding
and execution of instructions.
 PC, IR, MAR,MBR
 Program status word: Superset of condition code
registers.
CPU Function
62
 CPU must:
 Fetch instructions
 Interpret instructions
 Fetch data
 Process data
 Write data
 Hence, organization requirements are,
 ALU, control logic, temporary storage, and means to
move data in and out of CPU
CPU With Systems Bus
63
CPU Internal Structure
64
Single Bus Organization
65
Multiple Bus Organization
66
Multiple Bus Organization
67
What is an instruction set?
68
 The complete collection of instructions that are

understood by a CPU
 Machine Code
 Binary
 Usually represented by assembly codes
Elements of an Instruction
69
 Operation code (Op code)

 Do this
 Source Operand reference
 To this
 Result Operand reference
 Put the answer here
 Next Instruction Reference
 When you have done that, do this...
Where have all the Operands gone?(Areas of source
and result operands)
70
 Main memory (or virtual memory or cache)

 CPU register
 I/O device
Instruction Cycle State Diagram
71
Instruction Representation
72
 In machine code each instruction has a unique bit

pattern
 For human consumption (well, programmers
anyway) a symbolic representation is used
 e.g. ADD, SUB, LOAD
 Operands can also be represented in this way
 ADD A,B
Opcode Operand Reference Operand Reference
Instruction Types
73
 Ways of Classification
 According to function
 According to number of addresses
 Data processing
 Data storage (main memory)
 Data movement (I/O)
 Program flow control
Number of Addresses (a)
74
 3 addresses
 Operand 1, Operand 2, Result
 a = b + c;
 May be a forth - next instruction (usually implicit)
 Not common
 Needs very long words to hold everything
 2 addresses
 One address doubles as operand and result
 a=a+b
 Reduces length of instruction
 Requires some extra work
 Temporary storage to hold some results

Number of Addresses (b)
75
 1 address
 Implicit second address
 Usually a register (accumulator)
 Common on early machines
 0 (zero) addresses
 All addresses implicit
 Uses a stack. e.g. push a
 push b
 add
 pop c
 c=a+b
How Many Addresses
76
 More addresses
 More complex (powerful?) instructions
 More registers
 Inter-register operations are quicker
 Fewer instructions per program
 Fewer addresses
 Less complex (powerful?) instructions
 More instructions per program
 Faster fetch/execution of instructions
Instruction Set Design Decisions
77
(1)
 Operation repertoire
 How many ops?
 What can they do?
 How complex are they?
 Data types
 Instruction formats
 Length of op code field
 Number of addresses
Instruction Set Design
78
Decisions(2)
 Registers
 Number of CPU registers available
 Which operations can be performed on which
registers?
 Addressing modes
 RISC v CISC
Types of Operand
79
 Addresses
 Numbers
 Integer/floating point
 Characters
 ASCII etc.
 Logical Data
 Bits or flags
Types of Operation
80
 Data Transfer
 Arithmetic
 Logical
 Conversion
 I/O
 System Control
 Transfer of Control
CISC Complex Instruction Set
81
Compiler
 Very few general purpose registers
 Complex instruction set
 Difficult to pipeline
 Many addressing modes
 Multiple Cycle Execution
Eg. CISC
Approach
MUL A, B
CISC Architecture
82
Typical CISC Processor

CISC Advantages
83
 Advantages
 Microprogramming is easy to implement and much
less expensive than hard wiring a control unit.
 It is easy to add new commands into the chip without
changing the structure of the instruction set.
 This architecture makes the efficient use of main
memory since the complexity (or more capability) of
instruction allows to use less number of instructions to
achieve a given task.
 The compiler need not be very complicated, as the
micro program instruction sets can be written to match
the constructs of high level languages
CISC Disadvantages
84
 Disadvantages
 A new or succeeding versions of CISC processors
consists early generation processors in their subsets
(succeeding version). Therefore, chip hardware and
instruction set became complex with each generation
of the processor.
 The overall performance of the machine is reduced
because of slower clock speed.
 The complexity of hardware and on-chip software
included in CISC design to perform many functions.
RISC Reduced Instruction Set
85
Compiler
 Large number of general purpose registers
 Limited and simple instruction set
 Emphasis on optimising the instruction pipeline
 It optimizes the usage of register
 Simple addressing modes
 One Cycle Execution
 It simplifies the compiler design by using identical general
purpose registers which allows any register to be used in any
context.
 The number of bits used for the opcode is reduced
 In general there are 32 or more registers in the RISC.
RISC Architecture
86
Typical RISC Processor

RISC Pipeline
87
Eg. RISC
Approach
LOAD R1,3
LOAD R2, 5
PROD R1,R2
STORE R1, A
RISC Pipelining
RISC Advantages
88
 Small set of instructions of RISC, high-level language

compilers can produce more efficient code.
 Instead of using Stack, many RISC processors use the
registers for passing arguments and holding the local variables
 Very less number of instruction formats (less than four), a few
number of instructions (around 150) and a few addressing
modes (less than four) are needed.
 The speed of the operation can be maximized and the
execution time can be minimized
RISC Disadvantages
89
 The performance of a RISC processor depends on the code

that is being executed. The processor spends much time
waiting for first instruction result before it proceeds with next
subsequent instruction, when a compiler makes a poor job of
scheduling instruction execution.
 RISC processors require very fast memory systems to feed
various instructions. Typically, a large memory cache is
provided on the chip in most RISC based systems.
90
RIS
C Vs
CIS
C
Co Processor
91
 A computer co-processor is processor used to

supplement the function of primary processor.
 First seen on mainframe computers.
 Accelerate the system performance.
 Operations performed by co processors
 Floating point arithmetic
 Graphic & Signal processing.
 String processing.
 Encryption
 Crypto processing
 Network coprocessor
History of Co Processor
92
 Co-processor for floating point arithmetic first

appeared in desktop computers in 1970s.
 The coprocessors become common in 1980s and
into the early 1990s.
 Early 8 Bit and 16 Bit processor uses software to
carryout the floating point arithmetic operations.
 Math co-processor were popular purchase for users
of computer-aided design (CAD) software and
scientific and engineering calculations.
Network Co Processor
93
Nexperia Co Processor
94
Design Principles for Modern
Computers
95
 All Instructions Are Directly Executed by

Hardware
 Maximize the Rate at Which Instructions Are
Issued
 Instructions Should be Easy to Decode
 Only Loads and Stores Should Reference Memory
 Provide Plenty of Registers
Instruction-Level Parallelism(1)
96
A 5 Stage Pipeline
97
Dual 5 Stage Pipeline

98
Super Scalar Architecture

Processor-Level Parallelism(1)
99
Multiprocessors
Multicomputers
References
100
 Douglas Hall, “Microprocessors & Interfacing”, McGraw Hill, Revised

2nd Edition, 2006 ISBN 0- 07-100462-9
 A. Tanenbaum, ―Structured Computer Organization‖, Prentice Hall of
India, 1991 ISBN: 81 – 203 – 1553 – 7, 4th Edition
 Computer Architecture and Organization, John P Hays, 3nd Edition,
McGraw-Hill Publication, 2001,ISBN 0071004793
 W. Stallings, ―Computer Organization and Architecture: Designing for
performance‖, Pearson Education/ Prentice Hall of India, 2003, ISBN 978-
93-325-1870-4, 7th Edition.

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MIT Art Design & Technology University’s

MIT School of Engineering, Pune

COMPUTER ORGANIZATION &

Pins and Signals

Low order address bus; these are

When AD lines are used to transmit

When data are transmitted over AD lines

A16/S3, A17/S4, A18/S5, A19/S6

High order address bus. These are

Pins and Signals

BHE (Active Low)/S7 (Output)

Bus High Enable/Status

It is used to enable data onto the most

This pin signal indicates what mode the

RD (Read) (Active Low)

The signal is used for read operation.

Pins and Signals

This is the acknowledgement from the

The signal is active high.

Pins and Signals

Causes the processor to immediately

The clock input provides the basic timing

INTR Interrupt Request

This is a triggered input. This is sampled

The 8086 microprocessor can work in two

In the minimum mode of operation the

In the maximum mode the 8086 can work

Minimum or maximum mode operations

When this pin is high 8086 operates in

Pins and Signals

ALE (Address Latch Enable) Used to demultiplex the

Pins and Signals

HOLD Input signal to the processor form the bus masters

Usually used by the DMA controller to get the

HLDA (Hold Acknowledge) Acknowledge signal by the

The acknowledge is asserted high, when the

Pins and Signals

Pins and Signals

Pins and Signals

Code Segment Register

Data Segment Register

Segment Stack Segment Register

Points to the current stack.

Extra Segment Register

Segment Instruction Pointer

Always points to the next instruction to be executed within

So, this register contains the 16-bit offset address pointing

Its content is automatically incremented as the execution of

This is done in order to speed up the execution by overlapping

This mechanism is known as pipelining.

Accumulator Register (AX)

The I/O instructions use the AX or AL for inputting / outputting

Multiplication and Division instructions also use the AX or AL.

Base Register (BX)

Consists of two 8-bit registers BL and BH, which can be combined

BL in this case contains the low-order byte of the word, and BH

This is the only general purpose register whose contents can be

All memory references utilizing this register content for

Counter Register (CX)

When combined, CL register contains the low order byte of the

Instructions such as SHIFT, ROTATE and LOOP use the contents

Stack Pointer (SP) and Base Pointer (BP)

SP is used as an offset from the current SS during execution