HDL Lecture3

Hardware Description
Languages
Professor: Sci.D., Professor

Vazgen Melikyan
Synopsys University Courseware

Copyright © 2014 Synopsys, Inc. All rights reserved.
Hardware Description Languages
Lecture - 3
1 Developed By: Vazgen Melikyan
Course Overview
 The Role and Classification of HDLs

 1 lecture
 System Verilog
 2 lectures
 SystemC
 3 lectures
 Verilog
 4 lectures
 VHDL
 3 lectures
 Process of Synthesis
 2 lectures

Lecture - 3
Developed By: Vazgen Melikyan
2
System C

Lecture - 3
3 Developed By: Vazgen Melikyan
System Design Methodology
 System hardware is modeled on block and

signal (RTL) level
 Software and firmware are tested using
simulation before running on real device

Lecture - 3
4
Old Methodology
System Level Modeling

C/C++
VHDL/Verilog
Analysis
Simulation
Result
Refinement Synthesis

Lecture - 3
5
SystemC Methodology
SystemC Model
Simulation
Refinement
Synthesis

Lecture - 3
6
Drawbacks of Using Pure C++ As
HDL
 C++ does not support time sequenced events
 Hardware is concurrent which cannot be
described in C++
 C++ native data-types are not enough to
model hardware

Lecture - 3
7
Main Benefits of SystemC Over C++
 Timed sequenced operations

 Hardware data types
 Bit type, multi-valued logic type, etc.
 Concurrency
 Processes can be executed in parallel

Lecture - 3
8
Benefits of SystemC
 Provides system level and HDL modeling

capabilities
 Open source
 Used by many major companies
 Runs on both Windows and UNIX platforms

Lecture - 3
9
Introduction to SytemC
 SystemC is an extension to C++ without

changing the syntax

Lecture - 3
10
Definition of SystemC
 SystemC is not a separate language

 Essentially a C++ library
 New concepts and data types are introduced to
enable hierarchical hardware modeling
 Model of timing and event-driven simulations is
introduced
 Sequential in nature
 Allows description and integration of complex hardware and
software
Lecture - 3
11
SystemC Features

Lecture - 3
12
Core Concepts
 Modules
 Basic units of hierarchy
 Processes
 Concurrent threads of execution
 Events
 Control of the processes timing
 Channels
 Means of communication of modules
 Interfaces
 Definitions of features a channel must implement
 Ports
 Access points for modules to connect to channels
Lecture - 3
13
Modules
 Basic units of hierarchy

 Modules contain
 Ports
 Channel instances
 Internal data
 Member module instances (hierarchy)

Lecture - 3
14
Modules: Declaration
 Module declaration
SC_MODULE(module_name) {
// ports, logic, etc.
SC_CTOR {
// Module constructor
// contains process declaration, sensitivities, etc.
}
}
 SC_MODULE is defined as a macro so

module is a class inherited from sc_module
#define SC_MODULE (module_name) struct module_name: public sc_module

Lecture - 3
15
Module Instantiation
 Modules instantiated as standard C++ classes

 Instance name is passed to the constructor
SC_MODULE(Multiplier) {
// ports, logic, etc.
SC_CTOR {
// contains process declaration, sensitivities, etc.
}
}
Multiplier my_mul (“my_mul”); //Module instantiation

Lecture - 3
16
Channels, Interfaces and Ports
 Used by modules for communication

 Channels hold and transmit data
 Interfaces define operations that channels
provide
 Ports give access to channels
 Ports are bound to channels through interfaces

Lecture - 3
17
Connection
 Ports defined in modules bind to interfaces or ports (in

case of hierarchical channels)
 Channels provide actual connection and implement
necessary operations
 Interfaces define functions provided by channels
Hierarchical
Module 1 Module 2
channel
port
interface
Lecture - 3
18
Interface
 Is a set of functions which will be

implemented by the channel
 Defines only signatures of operations without
implementation
 Channels must implement all the functions to
implement interface
 Channels can implement multiple interfaces
 Multiple channels can be defined by the same
interface
Lecture - 3
19
Interface: Declaration
 Interface is an abstract class derived from sc_interface
 All functions are declared virtual
class interface_name: virtual public sc_interface
{
public:
virtual void function_name(int) = 0; // virtual functions
…
};
class int_variable_access: virtual public sc_interface

{
public:
virtual void assignValue(int) = 0; // assign value
virtual int getValue() = 0; // get value
};

Lecture - 3
20
Port
 Provides access to channels for modules

 Port specifies which interfaces it corresponds
to
 All ports are derived from: sc_port_base
 Ports have direction
 input sc_in
 output sc_out
 bidirectional sc_inout
Lecture - 3
21
Port: Declaration
 Syntax
 port_type<data_type> port_name
SC_MODULE(Multiplier) {
sc_in<int> a; // ports
sc_in<int> b;
sc_out<int> product;
//logic, internal data, etc.

SC_CTOR {
// process declaration, sensitivities, etc.
}
}

Lecture - 3
22
Port: Defining New Port Types
 SystemC provides template class to define

ports: sc_port
 sc_port takes two parameters
 An interface to which it can be connected
 Maximum number of interfaces that may be connected
to this port (default is 1) template<class IF, int N=1>
class sc_port: ….
{
public:
IF* operator->();
// member functions
}

Lecture - 3
23
Channel
 Connects modules
 Channels implement all the functions of
interface
 Two types of channels
 Primitive
 sc_signal, sc_fifo, sc_mutex, sc_semaphore
 Hierarchical
 Actually a module (modules, ports, channels contained within)

Lecture - 3
24
Channel: Declaration
class channel_name: public interface_name, public

sc_channel
{
public:
virtual void function1(int); //
implementation of interface methods
virtual void function2(int);
//ports
SC_CTOR(channel_name) { … } //channel
constructor
private:
…
}

Lecture - 3
25
Channels, Interfaces and Ports:
Example
class int_access: virtual public sc_interface
{
public:
virtual void assignValue(int) = 0; // assign value
virtual int getValue() = 0; // get value
};
class int_channel: public int_access, public sc_channel

{
public:
virtual void assignValue(int); // interface methods implemented in
channel
virtual int getValue();
sc_in<int> data_in; //ports

sc_out<int> data_out;
sc_in<bool> clock;
sc_out<bool> ready;
SC_CTOR(int_channel) { … } //module constructor

private:
…
}

Lecture - 3
26
Events
 Events (positive clock edge, etc.) can be

used in two ways
 Code execution waits for an event to fire
 Event is fired by executed code

Lecture - 3
27
Sensitivity
 Sensitivity defines list of events which will

trigger process
 Static
 Defined at declaration level
 Syntax:
sensitive << event_1 << event_2
 Dynamic
 Allows alteration of sensitivity during execution of a thread
 Syntax
wait(event);

Lecture - 3
28
Processes
 Run concurrently with other processes

 Sensitive to events
 Static sensitivity
 Dynamic sensitivity
 Registered in module constructor

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Processes: Types
 Processes
 Methods (sc_method)
 Threads (sc_thread)
 Clocked Threads (sc_cthread)

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Processes: Methods
 Methods
 Simply a C++ function
 Runs completely, then returns
 Cannot be terminated
 Dynamic sensitivity can be defined using
next_trigger() function

Lecture - 3
31
Processes: Threads
 Threads
 Used for processes not expected to halt
 Threads can be suspended using wait()
 wait() waits for event before continuing execution (static
sensitivity)
 wait() can be called with an argument to override default
sensitivity (dynamic sensitivity)
 Not synthesizable

Lecture - 3
32
Processes: Clocked Threads
 Clocked Threads
 Triggers at clock
 Do not have separate sensitivity
 Used for behavioral synthesis

Lecture - 3
33
Processes: Example
 Simple function can SC_MODULE(Multiplier)

{
be registered as sc_in<bool> A, B;
sc_out<bool> S;
process void mul()
 Processes must be {
S.write((A.read() * B.read()));
registered in module }
constructor SC_CTOR(Multiplier) {
SC_METHOD(mul); // process
sensitive << A << B; // sensitivity
}
};

Lecture - 3
34
SystemC Data Types
 SystemC Data Types

 C++ Built-in Types
 Bit and bit vector
 Four-state logic
 Fixed Precision ints
 Arbitrary Precision
 Fixed Point Types

Lecture - 3
35
SystemC Data Types: C++ Types
 C++ built-in types

 bool
 char
 int
 float
Not synthesizable
 strings
 pointers, references, etc.

Lecture - 3
36
SystemC Data Types: Logic Types
 Bit and Bit vector

 sc_bit, sc_bv<N>
 Four-state logic
 sc_logic,
 sc_lv<N>
 0: Logical 0
 1: Logical 1
 Z: High Impedance
 X: Unknown

Lecture - 3
37
SystemC Data Types: Integer Types
 Fixed Precision
 64 bit
 sc_int<N>
 sc_uint<N>
 Arbitrary Precision
 Up to 512 Bits
 sc_bigint<N>
 sc_biguint<N>

Lecture - 3
38
SystemC Data Types: Fixed Point
Types
 Fixed Point Types
 Useful in DSP applications
 Specify Quantization and Saturation Behavior
 sc_fixed<wl, iwl, q_mode, o_mode, n_bits>
 wl: Total WorD Length
 iwl: Integer Word Length
 q_mode: Quantization Mode
 o_mode: Overflow Mode
 n_bits: Number of Saturated Bits

Lecture - 3
39
SystemC Data types: Summary
Type Description
sc_logic Simple bit with 4 values(0/1/X/Z)
sc_int Signed Integer from 1-64 bits
sc_uint Unsigned Integer from 1-64 bits
sc_bigint Arbitrary size signed integer
sc_biguint Arbitrary size unsigned integer
sc_bv Arbitrary size 2-values vector
sc_lv Arbitrary size 4-values vector
sc_fixed Templated signed fixed point
sc_ufixed Templated unsigned fixed point
sc_fix Untemplated signed fixed point
sc_ufix Untemplated unsigned fixed point

Lecture - 3
40
SystemC Operators
 SystemC Operators
 C++ Built-in Types
 Bit selection
 Part Selection
 Bitwise
 Concatenation
 Integer Conversion

Lecture - 3
41
SystemC Operators: C++ Built In
 Equality and bitwise operators (==, <<, >>)

 For all data types
 Arithmetic and relational operators (+, -, <, >)
 Only for numeric data types
 Overloaded assignment operators
 Converts types during assignment, though some data may be
truncated
 e.g.: intVariable = floatValue;
 Increment Decrement
 Operators: ++, --
Lecture - 3
42
SystemC Operators: Bit selection
 Bit selection
 Access to a specific bit in a variable
 C++ operator [ ]
sc_int<32> intNumber;
intNumber[11] = true; // Setting bit 1 of intNumber to true

intNumber[15].to_bool(); // Reading bit 0

Lecture - 3
43
SystemC Operators: Part Selection
 Part Selection
 Access to a specific bit subset of bits in a variable.
 Available methods:
 range(int, int)
 C++ operator()
sc_int<8> intNumber = 5; // assigned value is 00000101

myInt.range(6, 4) = myInt.range(2, 0); // resulting value is 01010101
myInt(6, 4) = myInt.range(3, 1); // resulting value is 00100101

Lecture - 3
44
SystemC Operators: Bitwise
 Bitwise Reduction
 Performs bitwise operation on all bits in integer or vector
 Returns bool
 Operations:
 and_reduce() - Bitwise AND between all bits
 nand_reduce() - Bitwise NAND between all bits
 or_reduce() - Bitwise OR between all bits
 nor_reduce() - Bitwise NOR between all bits
 xor_reduce() - Bitwise XOR between all bits
 xnor_reduce() - Bitwise XNOR between all bits

Lecture - 3
45
SystemC Operators: Concatenation
 Concatenation
 Concatenates the bits of two variables together
 Available methods:
 concat(arg0, arg1)
 C++ comma operator “operator,”
sc_int<8> myInt1 = 5; // 00000101

sc_int<4> myInt2 = 3; // 0111
sc_int<8> myInt3 = concat(false, myInt2, myInt1.range(2,1), myInt2[0]);
// myInt3 = 00111101
//assignment to concatenation
(myInt2[2], myInt1.range(3,5)) = myInt3.range(3, 0);

Lecture - 3
46
SystemC Operators: Integer
Conversion
 Integer Conversion
 All SystemC data types
 accept C++ integer assignment
 convert to C++ integer types
 Conversion Methods
 to_int() - Convert to native int type
 to_uint() - Convert to native unsigned type
 to_long() - Convert to native long type
 to_ulong() - Convert to native unsigned long type
 to_uint64() - Convert to native 64-bit unsigned integer
 to_int64() - Convert to native 64-bit signed integer

Lecture - 3
47
SystemC Operators: Summary
Operators
Arithmetic +, -, *, /, %
Assignment =, +=, -=, *=, %=, & =
Equality ==, !=
Relational <, >, <=, >=
Auto-Inc/Dec ++, --
Bit selection [x]
Part select range()
Concatenation (,)
Bitwise ~, &, |, ^, >>, <<
Integer Conversion to_int(), to_uint(), to_long() etc.

Lecture - 3
48
Time Model
 Time value is defined using sc_time

(unsigned 64 bit integer)
 Units
 Femtoseconds (SC_FS)
 Picoseconds (SC_PS)
 Nanoseconds (SC_NS)
 Miliseconds (SC_US)
 Microseconds (SC_MS)
 Seconds (SC_SEC)
Lecture - 3
49
Time Model: Functions
 Functions for controlling simulation and

reporting time information:
 sc_stop()
 Stops simulation
 sc_start()
 Returns control to the main (sc_main() ) routine
 sc_time_stamp()
 Returns an sc_time object with the current simulation time
 sc_simulation_time()
 Returns a double value of current simulation time
Lecture - 3
50
Simulation
 Like main() in C++, in SystemC execution

starts with sc_main()
int sc_main (int argc, char* argv[])

{
sc_set_time_resolution (1, SC_US):
Multiplier mul(“mul”); // Top level instance
sc_start (500, SC_US); // Running the simulation

return (0);
}

Lecture - 3
51
Debugging
 Text based
 Uses console to output internal status
 Waveform Tracing
 Uses special tracing functions

Lecture - 3
52
Text-based Debugging: Simple
Output
 C++ “printf”
 Stream output
printf(“Started.”);
cout << “Thank you!\nExit.\n”;

Lecture - 3
53
Text-based Debugging: Constructor
 Debugging Constructor
 Used to debug class initialization issues
 name() method used to identify SystemC classes
SC_CTOR(Multiplier) {
cout << “Initializing Multiplier: “ << name() << endl;
...
...
}

Lecture - 3
54
Text-based Debugging: Special
Methods
 Special debugging methods available for all
SystemC objects:
 const char* name()
 Returns the name of the object
 const char* kind()
 Returns the object’s sub-class name
 void print(ostream& out)
 Prints the object’s name to the output stream
 void dump(ostream& out)
 Prints the objects diagnostic data to the output stream
Lecture - 3
55
Text-based Debugging: Example
SC_MODULE(ClockedModule)
{
sc_in<bool> A,B;
sc_in<bool> Clock;
void monitorInputs()
{
cout << “Time > A B" << endl;
while (true) //infinite loop
{
cout << sc_time_stamp() << “: A=";
cout << A.read() << ", B=";
cout << B.read() << endl;
wait(); // wait for next event
}
}
SC_CTOR(ClockedModule)
{
SC_THREAD(printInputs);
sensitive << Clock.pos();
}
}

Lecture - 3
56
Wave-form Tracing
 For wave-form tracing additional SystemC

statements need to be added to sc_main()
 Wave-form data written to file as simulation runs
 sc_create_vcd_trace_file()
 Declare and create the trace file
 sc_trace()
 Register signals or events for tracing
 Run the simulation
 sc_close_vcd_trace_file()
 Close the trace file

Lecture - 3
57
Wave-form Tracing: Example
int sc_main(int argc, char* argv[])
{
sc_set_time_resolution (1, SC_US):
Multiplier mul(“mul”);
// Setting up trace file

sc_trace_file* myTraceFile;
myTraceFile = sc_create_vcd_trace_file("traces");
((vcd_trace_file*) myTraceFile)->sc_set_vcd_time_unit(-9);
// Set time unit
// Register signals to be traced

sc_trace(myTraceFile, A , "A" );
sc_trace(myTraceFile, B , "B" );
sc_trace(myTraceFile, mul.C, “C");
// Running the simulation

sc_start (500, SC_US);
// Clossing trace file

sc_close_vcd_trace_file(myTraceFile);
return (0);
}

Lecture - 3
58
Lecture - 3
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Hardware Description

Professor: Sci.D., Professor

Synopsys University Courseware

 The Role and Classification of HDLs

Synopsys University Courseware

Synopsys University Courseware

 System hardware is modeled on block and

Synopsys University Courseware

System Level Modeling

Synopsys University Courseware

Synopsys University Courseware

Synopsys University Courseware

 Timed sequenced operations

Synopsys University Courseware

 Provides system level and HDL modeling

Synopsys University Courseware

 SystemC is an extension to C++ without

Synopsys University Courseware

 SystemC is not a separate language

Synopsys University Courseware

 Basic units of hierarchy

Synopsys University Courseware

 SC_MODULE is defined as a macro so

Synopsys University Courseware

 Modules instantiated as standard C++ classes

Synopsys University Courseware

 Used by modules for communication

Synopsys University Courseware

 Ports defined in modules bind to interfaces or ports (in

 Is a set of functions which will be

class int_variable_access: virtual public sc_interface

Synopsys University Courseware

 Provides access to channels for modules

//logic, internal data, etc.

Synopsys University Courseware

 SystemC provides template class to define

Synopsys University Courseware

Synopsys University Courseware

class channel_name: public interface_name, public

Synopsys University Courseware

class int_channel: public int_access, public sc_channel

sc_in<int> data_in; //ports

SC_CTOR(int_channel) { … } //module constructor

Synopsys University Courseware

 Events (positive clock edge, etc.) can be

Synopsys University Courseware

 Sensitivity defines list of events which will

Synopsys University Courseware

 Run concurrently with other processes

Synopsys University Courseware

Synopsys University Courseware

Synopsys University Courseware

Synopsys University Courseware

Synopsys University Courseware

 Simple function can SC_MODULE(Multiplier)

Synopsys University Courseware

 SystemC Data Types

Synopsys University Courseware

 C++ built-in types

Synopsys University Courseware

 Bit and Bit vector

Synopsys University Courseware

Synopsys University Courseware