Internship Presentation
VLSI SoC Design using Verilog HDL
Name: Suraj Patel
Roll No. : 2100910319008
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
PRESENTATION OUTLINE
1. Certificate of Internship
2. Objective of Internship
3. Introduction
4. Description of Project Implemented.
• Block diagram/Flow Chart
• Discussion on Hardware/Software results
5. Conclusion
CERTIFICATE OF INTERNSHIP
OBJECTIVE
• The objective of this internship was to strengthen the knowledge on chip design
process.
• It trained us on VLSI Technology, SoC Architecture and Design process, coding
for
synthesis and simulation. It also helped us with the concept of hardware
description language and basic concepts like data types and operators.
• Moreover it also trained us in advanced concepts like assignments,
procedural
blocks, synthesis coding style and test bench coding.
INTRODUCTION
VLSI
• Small Scale Integration (SSI) 1-10
• Medium Scale Integration (MSI) 10-100
• Large Scale Integration (LSI) 100-1000
• Very Large Scale Integration (VLSI) 1000-100000
• Ultra High Scale Integration (ULSI) >100000
VERILOG HDL
• Programming Language
• Hardware Description Language
• Understanding the Behavior of Language
• Its syntax is similar to C Language
• Easy to learn and use
• Verilog HDL is both a behavioral language and structural language.
• Verilog is case sensitive language.
HISTORY
• Verilog was created by Prabhu Goel, Phil Moorby, Chi-Lai Huang, and Douglas
Warmke between late 1983 and early 1984. Chi-Lai Huang had earlier worked
on a hardware description LALSD, a language developed by Professor S.Y.H.
Su, for his PhD work.
• Verilog 2001 Extensions to Verilog-95 were submitted back to IEEE to cover
few limitation of Verilog -95.
• Originally, Verilog was intended to describe and allow simulation.
• Today all EDA developer companies are using Verilog-2001.
• The foundations of Superlog and Vera were donated to Accellera , which later
become the IEEE standard 1800—2005: System Verilog.
ASIC vs FPGA
FPGA ASIC
Reconfigurable circuitry after Fixed circuitry for product’s lifespan.
manufacturing.
Suitable for digital designs only. Analog/mixed –signal circuitry can be
fully implemented.
Are typically larger than ASIC’s. Can be much smaller than FPGA devices.
Difficult to attain high –frequency rates. Operate at higher frequency rates.
Prototyping and validating with FPGA’s is Prototypes must be accurately validated
easier. to avoid design iterations.
Faster time-to-market ,high per unit Long time-to-market ,lower per unit
costs. costs.
DESIGN SOC
Design flow of SoC aims in the development of hardware and software of
SoC designs.
PROJECT
4-to-1 Multiplexer
4-to-1 Multiplexer
//4-to-1 Mux: Structural Verilog
module mux_4_to_1_st_v(S,D,Y);
input [1:0]S;
input [3:0]D;
output Y;
wire [1:0]not_s;
wire [0:3]N;
not
g0(not_s[0],S[0]),g1(not_s[1],S[1]);
and g2(N[0],not_s[0],not_s[1],D[0]),
g3(N[1],S[0],not_s[1],D[0]),
g4(N[2],not_s[0],S[1],D[0]),
g5(N[3],S[0],S[1],D[0]);
or g5(Y,N[0],N[1],N[2],N[3]);
endmodule
4-to-1 Multiplexer – Data Flow
//4-to-1 Mux: Dataflow description
module mux_4_to_1(S,D,Y);
input [1:0]S;
input [3:0]D;
output Y;
assign Y = (~S[1]&~S[0]&D[0])|(~S[1]&S[0]&D[1])
|(S[1]&~S[0]&D[2])|(S[1]&S[0]&D[3]);
endmodule
//4-to-1 Mux: Conditional Dataflow description
module mux_4_to_1(S,D,Y);
input [1:0]S;
input [3:0]D;
output Y;
assign Y = (S==2’b00)?D[0] : (S==2’b01)?D[1] :
(S==2’b10)?D[2] : (S==2’b11)?D[3]:1’bx;;
endmodule
4-to-1 Multiplexer
//4-to-1 Mux: Dataflow Verilog Description
module mux_4_to_1(S,D,Y);
input [1:0]S;
input [3:0]D;
output Y;
assign Y=S[1]?(S[0]?D[3]:D[2]):(S[0]?
D[1]:D[0]);
endmodule
CONCLUSION
The goal was to study the various materials used in VLSI technology.
The study reveals that present scaling of the CMOS technology to nano
dimensions will have to limit at some point and make further scaling may
be impossible while retaining all the electrical characteristics of the
devices.
VLSI is suitable for fabrication of large number of components on a single
chip.
VHDL/VERILOG is used for digital circuit designing and to validate the
design and check the design specification.
Thank you !
