Weekly Assessment

PD INPUTS
AND
FLOOR PLAN
Presented by:
Apoorva

Jigar Kumar Luhar

Susmita Bera
 CONTENTS
❑ PD inputs
❑ Floor planning

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PD inputs

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 Netlist
❑ Textual description of circuits components (like logic gates, combinational
circuits, sequential circuits), so netlist is a collection of gates.

❑ It contains the logical connectivity of all the cells.

❑ It can also be a collection of resistors, capacitors or transistors.

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 Synopsys Design Constraints(SDC) :

❑ These are timing constraints and used to meet the timings.

constraints are :
❑ create clock definition
❑ generated clock definition
❑ Virtual clock
❑ input delay
❑ output delay

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 Timing library/logical library (.lib):
❑ It contains timing information of standard cells, soft macros, hard macros.

❑ It contains Functionality information of standard cells and soft macros.

❑ Timing information like cell delay setup, hold, recovery, removal are
present.

❑ Design rules like max tran, max cap, max fanout, min cap are present

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 Timing library/logical library (.lib):
❑ Cell delay is a function of input transition and output load and is
calculated based on lookup tables.It is calculated by Nonlinear Delay
Mode(NLDM) and composite current source(CCS)models.

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 Physical Library(.lef) :
❑ It contains physical information of standard cells, macros, pads.

❑ Contain the name of the pin, pin location, pin layers, direction of pin(in,
out,inout), uses of pin (Signal, Power, Ground) site row, height and width
of the pin and cell.

❑ Contain the height of standard cell placement rows.

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 Physical Library(.lef) :
❑ .lef contains two types of views

❑ CELL view: it is a full layout of the block and used at the time of tape out.

❑ FRAM view: this is an abstract view that has only the pins, metals, via and
blockages that are used in Placement & Route stages.

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 Technology File :

❑ Contain the number of metal layers and vias and their name and
conventions.

❑ Design rules for metal layers like the width of metal layer and spacing
between two metal layers.

❑ Metal layers resistance and capacitance as well as routing grid.

❑ Unit, precision, color, and pattern of metal layer and via.

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 TLU+(Table Lookup)
❑ It is a table containing wire cap at diffrent net length and spacing.

❑ contain RC coeficients for specific technology.

❑ TLU+ files are extracted or generated from ITF(contains interconnect

details) file results.

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 TLU+(Table Lookup)

❑ The main function of this files are--

[a] . Extracted R, C parasitics of metal per unit length

[b] . These RC parasitics are used for calculating net delays.
[c]. If TLU+ files are not present these R,C parasitics extracted from.ITF files
[d]. For loading of TLU+ we have to load 3 files: 1. TLU+ 2. Min TLU+ 3. Max
TLU+
[e]. Map file maps the .itf file and .tf files of the layer and via names.

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 Floor planning
❑ In physical design, the first step in RTL-to-GDSII design is floor planning.
❑ Floorplan is one the critical & important step in Physical design. Quality
of your Chip / Design implementation depends on how good is the
Floorplan.
❑ Floorplan control Parameters :
1. Aspect Ratio
2. Utilization Factor = (Netlist Area) / Total Core Area
Netlist Area = standard cell area + macro area

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 Floor plan Inputs:
❑ Synthesis Netlist
❑ Physical Libraries
❑ Logic Libraries
❑ Timing constraints
❑ Power requirement
❑ Floor planning control parameters.

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 Floorplan Requirements
1. Basic design understating
2. Data flow diagram (DFA / Analyse logic connectivity in Synopsys ICC)
3. Integration guidelines
4. IO / Pin placement requirements
5. Special requirements from Full Chip floorplan
6. MV / LP requirements. Understanding of PDs & Vas

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 Types of Partitions/ Blocks
1. Memory intensive digital cores, graphic cores
2. Partitions / Blocks with analog Hard IPs
3. DDR & other High Speed Interface partitions / blocks / sub-systems
4. Channel partitions

❑ Partition with different critical task

1. Timing critical
2. Routing critical / Congestion
3. Blocks with complex Clock structure

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 Floorplan Techniques
1. Abutted (All inter block pin connections are done through FTs)
2. Non abutted (Channel based. All inter block pin connections are routed
in channels)
3. Mix of both – partially abutted with some channels

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 Floorplan Steps
1. Size & shape of the block (Usually provided by FC floorplan)
2. Voltage area creation (Power domains)
3. IO placement
4. Creating standard cell rows
5. Macro-placement
6. Adding routing & placement blockages (as required)
7. Adding power switches (Daisy chain)
8. Creating Power Mesh
9. Adding physical cells (Well taps, End Caps etc)
10.Placing & qualifying pushdown cells
11.Creating bounds / plan groups / density screens

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 Floorplan steps
1. Size & shape of the block: In most of the case, block size & shape is
decided by FC floorplan. Rectangle/Square shape is best in terms of
floorplan & further design closure.
2. Voltage area creation: In multi-voltage & multi power domain designs,
voltage areas are required to guide the tool to understand different
domains.
Two methods to create voltage area:
a) Abutted voltage area
b) Non-abutted voltage area

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 Floorplan steps
3. IO placement: IOs / Pins are placed at the boundary of the block. Usually
pin placement information is pushed down from FC floorplan.
4. Creating standard cell row: Rows area created in the design using cell-
site (unit / basic). Rows aid in systematic placement of standard cells. And
standard cell power routes done considering rows.

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 Macro Placement
❑ Steps:
1. Understand Pins & Orientation requirements of Macros
2. Follow data flow /hierarchy to place the Macros. Make use of reference
floorplan if available
3. All the pins of the Macros should point towards the core logic
4. Channels between macros should be big enough to accommodate all
routing requirements & should get a minimum of one pair VDD & VSS
power grids in the channel

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 Macro placement checks
❑ All macros should be placed at the boundary
❑ Check the orientation & pin directions of all macros
❑ Spacing between macros should be enough for routing & power grid
❑ Macros should not block partition level pins
❑ Less congestion & good timing QoR – These cannot be achieved in one
shot, but need few iterations

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 6.Adding placement & routing blockages
❑ Buffer only blockages are added in channels between macros.
❑ Partial placement blockages can be added between the channels
blocking sequential cells. Partial blockages are added in congestion
prone areas/notches/corners.

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 7.Adding Power switches
❑ Power switches are MT-CMOS (multi-threshold) cells, which will have
very high threshold voltage when device is OFF & very low threshold
voltage when device is on.
❑ A strong network of power switches connected in daisy chain fashion
will be inserted in the design

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 8.Adding special cells
❑ Special cells are Well Taps, EndCaps, Spare Cells, Metal ECO-able cells
etc.
❑ Well-taps cells are added in partition/chip level to tie the wells to
VDD/VSS.
❑ End Cap Cells ensure proper terminations of rows, so that no DRC are
created. This is a physical-only cell.
❑ Spare cells are extra cells placed in your layout in anticipation of a future
ECO(Engineering change order).

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 Floorplan Checks
❑ Check PG connections (For macros & pre-placed cells only)
❑ LP / MV checks on floorplan database
❑ Check the power connections to all Macros, specially analog/special
macros if any
❑ All the macros should be placed at the boundary
❑ There should not be any notches / thin channels. If unavoidable, proper
blockages has to be added
❑ Remove all unnecessary placement blockages & routing blockages
❑ Check power connection to power switches
❑ Check power mesh in different voltage area voltage area
❑ Check pin-layers & check layer directions

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 Floorplanning Algorithms
Several broad classes of algorithms:

❑ Integer programming based

❑ Rectangular dual graph based
❑ Hierarchical tree based
❑ Simulated annealing based–Other variations

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 Integer Linear Programming Formulation
❑ The problem is modeled as a set of linear equations using 0/1 integer
variables.
❑ ILP solver used to obtain optimal solution based on a defined cost
function.
❑ Can be use only for small problem instances
-Very high computional complexity.

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 Rectangular Dual-Graph Approach
Basic Concept:
❑ Output of partitioning algorithms represented by a graph.
❑ –Floorplans can be obtained by converting the graph into
❑ its rectangular dual.

The rectangular dual of a graph satisfies the following properties:

❑ – Each vertex corresponds to a distinct rectangle.
❑ – For every edge, the corresponding rectangles are adjacent.

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 Hierarchical Approach
Widely used approach to floorplanning.
❑ Based on a divide-and-conquer paradigm.
❑ At each level of the hierarchy, only a small number of rectangles are
considered.

A small graph, and all possible floorplans.

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 Simulated Annealing
Important issues in the design of a simulated annealing optimization
problem:
❑ 1. The solution space.
❑ 2. The movement from one solution to another.
❑ 3. The cost evaluation function.

A solution by Wong & Liu is applicable to sliceable floorplans only.

❑ – Floorplan can be represented by a tree.
❑ – Postfix notations used for easy representation and
❑ manipulation.

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 Floor plan Outputs:
❑ Die/block Area
❑ I/O placed
❑ Macros Placed
❑ Power Grid designed
❑ Power Pre-routing
❑ Standard Cell Placement Areas

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