NEED OF DFT

Presented by
YAMINI THOKALA
OVERVIEW
 HISTORY
 INTRODUCTION TO TESTING
 DESIGN FLOW OF VLSI
 WHAT IS DFT ? WHY DFT ?
 ADVANTAGES, DISADVANTAGES & GOALS OF DFT
 DIFFERENCE B/W DV AND DFT
HISTORY
Progress From SSI to VLSI
 SSI - Number of transistors in IC is less than 50.
 MSI - Number of transistors in IC is between 50 and
5000.
 LSI - Number of transistors in IC is between 5000
and 1 lakh.
 VLSI - Number of transistors in IC is greater than 1
lakh.
Moore’s law and feature size
 Moore’s law states that number of transistors in IC
will be doubled for every 18 months.
 Feature size means steady decrease of dimensions
of transistors.
 Reduction in feature size results in increased
operating frequency and clock speeds.
 The reduction in feature size (less than 100 nm)
increases the probability of manufacturing defects in
IC which result in a faulty chip.
INTRODUCTION TO TESTING
Electronic Testing
• IC testing, PCB testing and System testing are done
at various stages of manufacturing. It is done not
only to detect faults but also to repair those faults at
those stages. Hence VLSI testing is important .
• RULE OF TEN : The cost of detecting a faulty IC
increases by an order of magnitude 10 as we move
through each stage of manufacturing.
Testing during VLSI Life Cycle

Input 1 Output 1

Output
Input test Circuit Pass/Fail
response
stimuli under test
analysis
Input n Output n
VLSI Development Process
 Design verification is a predictive analysis that ensures
that the synthesized design will perform the required
functions when manufactured.
 Wafer Test : Testing performed during the manufacturing
process is to test the ICs fabricated on the wafer in order to
determine which devices are defective.
 (Wafer is a thin slice of semiconductor material used in
electronics for the fabrication of integrated circuits)
 Package Test : The packaged devices are retested to
eliminate those devices that may have been damaged
during the packaging process.
 Finaltesting : It includes measurement of such
parameters as input/output timing specifications, voltage,
and current. It is done to maintain QA.
 Inaddition, Burn-in or Stress testing is often performed
where chips are subjected to high temperatures and
supply voltage.
 Failure mode analysis (FMA) is typically used at all
stages of IC manufacturing testing to identify
improvements to processes that will result in an increase
in the number of defect-free devices produced.
VLSI DESIGN FLOW

DFT

fFabrication
 Behavioural level description is simulated to determine if it
is functionally equivalent to the specification.
 RTL which contains more structural information in terms of
the sequential and combinational logic functions.
 A logical-level implementation is automatically synthesized
from the RTL description to produce the Gate-level design.
 Physical level is done to obtain the physical placement and
interconnection of the transistors in the VLSI device .
Manufacturing defects

 Two lines in close vicinity to be shorted.

 Line is broken(open).
 A specific junction may not have been fabricated
correctly.
We can check the defect either by checking the final
output or by checking individual components
separately.
What is DFT ?
 DFT is a technique, which facilitates a design to
become testable after production.
 It
is an extra logic which we put in normal design
which helps in post production testing.
 Post production testing is necessary because the
process of manufacturing is not 100% error free.
 There are defects in silicon which contribute towards
the errors introduced in the physical device.
 Thechip will not work as per the specifications if
there are any errors introduced in the fabrication.
 But the question is how to detect the errors
introduced in production process.
Why DFT ?
 To run functionality tests on million physical devices
manufactured, it is time consuming.
 There was a need to device some method.
 Without running full exhaustive tests on the physical
device.
 Which make us believe the device is manufactured
correctly. DFT is answer for that.
 DFT is a technique which only detects that a physical
device is faulty or is not faulty.
 After post production test is done on physical device,
if it is found faulty, trash it, don’t ship to customers.
 If it is found to be good, ship it to customers.
 It
reduces time from 3 months to 3 days to test
million chips, if DFT is used.
Example:
Controllability and Observability

 Control any of the inputs to a ‘0’.

 Control both the inputs to ‘1’.
 Observe the value at the output of ‘and’ gate.
Advantages of DFT
 DFT increases ability to measure the quality.
 It generates the necessary vectors easily.
 Reduces tester complexity.
 Reduces tester time.
 Reduces tester requirements.
Disadvantages of DFT
 It adds complication to the design flow.
 It increases power, area, timing and package pins.
 It adds risk to the design schedule .
Goals of DFT
 To improve
• Controllability
• Observability
• Predictability
DIFFERENCE B/W DV AND DFT
 DV verifies correctness of design.
 DFT verifies correctness of manufactured hardware.
 DV is performed by simulation, hardware emulation
or formal methods.
 DFT is performed in 2 steps:
• Test generation
• Test application
 DV is performed once prior to manufacturing.
 DFT is performed on every manufactured device.
 DV is responsible for quality of design.
 DFT is responsible for quality of devices.
THANK YOU