Iterative Architecture AES for Secure VLSI based

System Design
Abstract
In this digital age of communication, private and
confidential data is exchanged over internet and
stored in digital mediums. This data is constantly
under increasing threat. Encryption is one of the
techniques to protect sensitive data. AES is
considered to be one of most capable encryption
algorithm in cryptography. AES can be implemented
in hardware or software. Hardware implementation
would be faster and secure as compared to
software implementation. This paper explains
iterative architecture implementation of AES using
VerilogHDL
 Introduction to AES
Security is the major concern in today’s data handling.
Several cryptographic algorithms are developed for
protecting data communication in computer network.
The Advanced Encryption Standard (AES) is a computer
security standard issued by the National Institute of
Standards and Technology (NIST) intended for protecting
electronic data. Federal Information Processing
Standards (FIPS) Publication 197 defines specification of
AES. The AES cryptography algorithm can be used to
encrypt or decrypt blocks of 128 bits using cipher keys of
128, 196 or 256 bits wide (AES128, AES196, and AES256)
 AES ALGORITHAM
The AES in present work operates on 128 bits
which are considered in 4X4 bytes array. Each
array is called as state. The size of input block,
output block is 128 bits represented by four
columns of matrix. This gives Nb=4, which shows
4bytes or 32 bits in state matrix. The length of
cipher key is ‘K’. The possible length is 128,192
or256 bits. This gives Nk= 4, 6 or 8, which shows
number of columns in Cipher Key Array.
• 1. Key Expansion. Round keys are derived from the cipher
• key using the Rijndael’s
• 2. Initial Round. AddRoundKey —each byte of the state is
• combined with the round key using a bit-wise operation.
• 3. Middle Rounds. Nr = 1 till Nr-1 Repeatedly perform the
• following transformations:
• 1. SubBytes —a non-linear substitution step where
• each byte is replaced with another according to a
• lookup table.
• 2. ShiftRows—a transposition step where each row of
• the state is shifted cyclically a certain number of
• steps.
• 3. MixColumns—a mixing operation which operates
• on the columns of the state, combining the four bytes
• in each column.
• 4. AddRoundKey—same as described above.
• 4. Final Round (no MixColumns)
• 1. SubBytes—same as described above.
• 2. ShiftRows—same as described above.
• 3. AddRoundKey—same as described above.
Encryption Processing Blocks
 Technology
• VLSI:
• Very-large-scale integration (VLSI) is the
process of creating an integrated circuit (IC) by
combining thousands of transistors into a
single chip. VLSI began in the 1970s when
complex semiconductor and communication
technologies were being developed. The
microprocessor is a VLSIdevice.
 Tools Used
• Software :
Xilinx14.5

Language:
Verilog HDL
OUTPUT RESULTS
TOP LEVEL BLOCK
RTL SCHEMATIC
SIMULATION
 Conclusion
The iterative design implemented in this work
gives symmetric encryption and decryption
cycles. The encryption process is slow
compare to decryption. The area requirement
in VLSI based design is at prime. Iterative
design will reuse same hardware in each
round which will consume less area. The
crypto core implemented is as per Standard
AES.