DATA PATH FOR JUMP

STATEMENT CB.SC.U4AIE2310
IN MIPS 4
EOC 2

ARCHITECTURE
MIPS ARCHITECTURE
MIPS is implementation of a ISC
architecture

Instruction Set Architecture (ISA)

A interface between a user and a

microprocessor
Instruction set

ISA includes:Rules for using instructions -Mnemonics,

functionality, addressing modes
Instruction encoding
MIPS CHIP ARCHITECTURE
JUMP
 J Instruction:The J instruction branches the PC by a specified offset
 It's syntax is: J offset.
 The jump command uses the 26 BITs to create a full memory address like this: bits 31-28
of PC + Target address + 00 . We will add a Shift-Left-2 to shift the target address two
places, effectively adding two zeros on the right. It will receive 26 bits (LSB) from the
instruction and produce a 28 bit result. We will also splice in the 4 leftmost (MSB) bits of
the PC+4 We will thereby obtain a 32bit address.
DATA PATH STEPS IN MIPS
1. Fetch Stage:
The instruction containing the jump address (26 bits in the instruction's lower part) is fetched from memory.
The program counter (PC) is incremented by 4 to point to the next instruction in sequence (PC+4).
2. Decode Stage:
The fetched instruction is decoded, and the opcode field (bits 31-26) is identified as a jump instruction.
3. Execute Stage:
Shift Left 2: The 26-bit target address from the instruction is shifted left by two bits, appending two
zeros at the least significant end, resulting in a 28-bit value.
PC+4 Addition: The current PC value (already incremented by 4 in the fetch stage) is added to 4 again,
resulting in the address of the next instruction in sequence (PC+8).
Jump Control: The Jump control signal is set to 1
Mux Selection: The jump multiplexer selects the combined output of the Shift Left 2 unit (28 bits) and
the PC+4 unit (4 bits), forming a 32-bit jump address.
Write Back Stage: The selected 32-bit jump address from the mux is written to the PC register,
effectively changing the program flow to the new instruction pointed to by the jump address.
 DATA PATH OF JUMP
 The pc's value, as well as a fixed value necessary to
increase the PC by one cycle are passed into the adder.
The address of the instruction to be executed is passed
to the INSTRUCTION MEMORY.
 The adder performs an add operation to determine the
next PC value. On the other hand, the instruction is
decoded by the INSTRUCTION MEMORY.
 The decoded instruction is split into different
corresponding segments.

https://www3.ntu.edu.sg/home/smitha/fyp_gerald/jmpinstruction.html
 DATA PATH OF JUMP
 The jump target is sent to the shifter, and the
opcode is sent to the control unit.
 The shifter performs a shift left 2 operation on the
jump target. The Command Unit identifies the
type of instruction it is via the opcode.
 The shifter and the adder sends their new values
to the concatenator.
 The concatenator sends the new pc value to the
pc.

https://www3.ntu.edu.sg/home/smitha/fyp_gerald/jmpinstruction.html
THANK YOU