“8086 Interrupts”

in
[ Microprocessor Systems and Interfacing ]

Lecture-11

M. M. Yasin
myasin@cuisahiwal.edu.pk
 “8086 Interrupts”
Introduction
Definition
An interrupt is the method of processing the microprocessor(µP)
by some source.
When an interrupt occurs,
It causes a temporary halt in the current execution of any
program(run by the µP).
Then,
Microprocessor responds to the interrupt with an interrupt
service routine, which is a short program or subroutine that
instructs the microprocessor on how to handle that interrupt.
Note: At the end of each instruction cycle, the 8086 checks to see if any
interrupt has been requested.
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 “8086 Interrupts”
Introduction
Interrupts can be categorized/classified in different ways.
For example,
A. w.r.t. source. i.e., Hardware/Software/Error condition.
B. Maskable / Non-maskable interrupts.
C. Internal(inside the µP) / External interrupts.
D. Synchronous / Asynchronous interrupts.

Note: We will discuss (A) and (B) only.

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 “8086 Interrupts”
A. Interrupt classification w.r.t. SOURCE
An 8086 interrupt can come from any one of three sources:
1. Execution of interrupt instruction (INT)  Software Interrupt.

2. Interrupt (INTR) input pin OR Non-maskable interrupt input pin

(NMI)  Hardware Interrupt.

3. Error condition produced in the 8086 by the execution of an

instruction  For example, divide-by-zero error.

Note: 1 Software instruction (INT) for interrupt,

2 Hardware pins (INTR, NMI) for interrupt, and
1 Flag Bit (IF) in the Flag Register for interrupt
are available in 8086/8088 microprocessor.
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 “8086 Interrupts”
1. Software Interrupt Instructions
There are instructions in 8086 which cause an interrupt.
They are INT instructions with type number specified.
For example,
INT 3h  Break Point Interrupt instruction.
INT 20h  Exit to operating system.
INT 1Ah  Get system time.
INT 33h  Mouse initialization.
INT 12h  Get memory size.

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 “8086 Interrupts”
2. Hardware Interrupt
The primary sources of interrupts are the PCs timer chip,
keyboard, serial ports, parallel ports, disk drives, CMOS real-
time clock, mouse, sound cards, and other peripheral devices.

3. Interrupt generated due to Error condition

(produced by the execution of an instruction)
For example, divide by zero, overflow, illegal opcode, invalid
memory access error… etc.

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 “8086 Interrupts”
B. Interrupt classification w.r.t. TYPE
Following is another way to classify interrupts.
We call it as types of interrupts.

1. Non-maskable: It requires an immediate response by

microprocessor, usually used for serious circumstances like
power failure.

2. Maskable: Microprocessor can ignore it depending upon

some predetermined conditions.

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 “8086 Interrupts”
1. Non-Maskable Interrupt (NMI)
The processor provides a single non-maskable interrupt pin
(NMI) which has higher priority than the maskable interrupt
request pin (INTR). A typical use would be to activate a power
failure routine, Reset, Clock Monitor… etc.

Reset Interrupt – An NMI example

Processor initialization or start up is accomplished with
activation (HIGH) of the RESET pin.
The 8086 RESET is required to be HIGH for greater than 4 CLK
cycles.
The 8086 will terminate operations on the high-going edge of
RESET and will remain inactive as long as RESET is HIGH.

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 “8086 Interrupts”
Reset Interrupt – An NMI example
The low-going transition of RESET triggers an internal reset
sequence for approximately 10 CLK cycles. After this interval
the 8086 operates normally beginning with the instruction in
absolute location FFFF0H.

Table: Process initialization register content

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 “8086 Interrupts”
2. Maskable Interrupt
Whenever an external signal activates the INTR pin, the
microprocessor will be interrupted only if interrupts are
enabled using set interrupt Flag instruction.
If the interrupts are disabled using clear interrupt Flag
instruction, the microprocessor will not get interrupted even
if INTR is activated. That is, INTR can be masked.
Extra: INTR is a non vectored interrupt, which means, the 8086 does not
know where to branch to service the interrupt. The 8086 has to be told by
an external device like a Programmable Interrupt controller regarding the
branch.

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 “8086 Interrupts”

Placement/Organization of Interrupt Service Routines

• Since µP handles an interrupt by running a short program or
subroutine, called an Interrupt Service Routine(ISR).

• And for every source, there is a separate ISR.

• Therefore, all of these ISRs must be placed somewhere in

memory.

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 “8086 Interrupts”

Placement/Organization of Interrupt Service Routines

• In an 8086 system, the first 1KB.i.e., (00000H to 003FFH) or (0 to
1023) of memory is reserved for storing the addresses of the
interrupt service routines (ISRs).

• This reserved memory is known as Interrupt vector table (IVT)

or interrupt pointer table (IPT).

• IVTs / IPTs contain only the starting addresses of the ISRs.

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 “8086 Interrupts”
Placement/Organization of Interrupt Service Routines
• Each interrupt vector takes up 4 bytes to point to one
particular ISR. (Why 4 bytes ??)

• This 4-byte interrupt vector is identified by a number.

Intel calls this number as a type of the interrupt.
For example, INT 21H.
Here 21h is the type/number of the interrupt.

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 “8086 Interrupts”
Placement/Organization of Interrupt Service Routines

Question-1: What would happen if 2 interrupts occur at the

same time. Which interrupt would be handled by the
microprocessor first.
Question-2: How many ISR addresses can be stored in 1KB of
memory?

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 “8086 Interrupts”
Placement/Organization of Interrupt Service Routines
Answer-1: Lowest the number/type, highest the priority of an
interrupt. For example,
Type 0 identifies the highest-priority.
Type 255 identifies the lowest- priority interrupt.
Answer-2: The 80x86 chips allow up to 256 vectored
interrupts. This means that you can have up to 256 different
sources for an interrupt and the 80x86 will directly call the
service routine for that interrupt without any software
processing.
(This is in contrast to non-vectored interrupts that transfer control directly
to a single interrupt service routine, regardless of the interrupt source).

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 “8086 Interrupts”
Interrupt Vector Table Details
The 80x86 provides a 256 entry interrupt vector table
beginning at address 0:0 in memory.
This is a 1KB table containing 256 4-byte entries.

Each entry(of 4-byte size) in this table contains a segmented

address(segment[CS]:offset[IP]) that points to the interrupt
service routine in memory.

Each entry or interrupt-vector consists of 4 bytes:

Lowest 2 bytes are for IP address (with lower byte at lower address)
and,
Highest 2 bytes are for CS (with lower byte at lower address).

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 “8086 Interrupts”

Placement/Organization of Interrupt Service Routines

These 256 vectored-interrupts are grouped as follows:
1. INT 0  4: Dedicated to specific interrupts, (details in
the next slide).
2. INT 5  31: Reserved by Intel for use in future µPs.
3. INT 32  255: Available to use for HW/SW interrupts.

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 “8086 Interrupts”
Details of INT 0  4
INT 0: Known as divide by zero interrupt. For cases where the
quotient becomes particularly large to be placed.
INT 1: Known as single step interrupt. This type of interrupt is
primarily used for debugging purposes in assembly language.
INT 2: Also known as Non-Maskable NMI interrupt. These
type of interrupts are used for emergency scenarios such as
power failure.
INT 3: Breakpoint interrupts. When this interrupt occurs, a
program would execute up to its break point.
INT 4: Also known as overflow interrupt, is generally existent
after an arithmetic operation was performed.
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 “8086 Interrupts”
What happens when an Interrupt occurs
When an interrupt occurs, regardless of the source, the 80x86
does the following:
1. The CPU pushes the flags register onto the stack.
2. The CPU pushes a far return address (segment:offset) onto
the stack, segment value first.
3. The CPU determines the cause of the interrupt (i.e., the
interrupt number) and fetches the four byte interrupt vector
from address 0:vector*4.
– The interrupt type N is sent to the Central Processor Unit (CPU) via
the Data bus from the hardware interface.
– The interrupt vector contents are fetched, from (4 x N) and then
placed into the IP and from (4 x N +2) into the CS.

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 “8086 Interrupts”

4. The CPU transfers control to the routine specified by the

interrupt vector table entry.

What happens when an Interrupt Service Routine finishes…

When the interrupt service routine wants to return control, it
must execute an IRET (interrupt return) instruction.
The interrupt return pops the (1) Return Address and (2) Flags
off the stack.

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 “8086 Interrupts”

Barry B. Brey Book:

Everyone must go through the following pages:

Chapter 12: Interrupts

Topics: The Purpose of Interrupts,
Interrupts,
Interrupt Instructions
Pages: 451  455

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