80386DX Processor

Virtual Memory Management

1. Physical Memory is the total memory that can be directly connected to the
CPU using its address bus
2. Since 80386 microprocessor has a 32 bit address bus, the total physical
memory that can be connected is 2^32=4GB
3. Virtual memory is the total memory space that can be addressed by the CPU
registers
4. Virtual memory is basically the combination of 16 bit segment register and a
32 bit offset register
5. In Real Mode, the segment register gives the starting address of the segment
6. But in Protected Mode, the segment register just gives a selector which
selects a Descriptor for the segment
7. Though the selector is of 16 bits, only 14 bits are used as two bits give the
privilege level used for protection.
8. Each selector value corresponds to a different segment. Hence there can be
max 2^14 segments
Virtual Memory Management
9. The locations within the segment are identified by their offset addresses. Since
offset addresses are 32 bit, each segment can be max 2^32 = 4 GB.

10. Hence the max total Virtual Memory that can be accessed

= Max number of Segments * Max size of each segment = 2^14 * 2^32 = 2^46

= 64 TB

11. Out of 14 bits of the selector, one bit is used as a table identifier (T1) if T1 = 1
then use LDT, T1 = 0 then use GDT

12. So basically there are 2^13 ie. 8K Descriptors in LDT and 8K Descriptors in
GDT
Virtual Memory Management
Virtual Memory Management
13. This means the total 64 TB Virtual space is divided into 32 TB of Global space
and 32 TB of Local Space

14. The total 48 bit address having 16 bit segment address and 32 bit offset
address is called Virtual address . It is converted into 32 bit physical address using
two translations: Segment translation (Compulsory) and page translation (optional)

15. Segment translations converts 48 bit Virtual address into 32 bit Linear Address
which is further converted into a 32 bit Physical address by Page Translation
80386 : Segment Translation
80386 : Segment Translation
1. The Virtual Address is given by a Segment Register (16) and an Offset
Register (32)
2. First the Segment Register is examined
a. It gives a 13 bit index (Selector) which leads to a descriptor in LDT or in GDT, depending upon
the TI bit. If T1 = 1 the LDT, if T1 = 0 then GDT
3. Using the specified index the descriptor is accessed from LDT of GDT
4. This Descriptor is copied into an on chip Segment Descriptor Cache. It is of 8
bytes
5. There is a bit “P” in the Descriptor
6. If P = 1, the Segment is Present in the Physical Memory
7. Then the base address (starting address) of the segment is available in the
Descriptor
8. If “P” = 0 the Segment is Not Present in the Physical Memory
80386 : Segment Translation
9. Now the Memory Management Unit copies the segment from Virtual Memory to
Physical Memory, makes the “P” bit = 1 in the Descriptor and stores its base
address into the Descriptor for further use
10. To this base address, the 32-bit offset address is added
11. This finally gives the 32-bit Linear Address of the desired Location
12. For subsequent access to the same segment, the Descriptor which is already
cached is used
13. The “P” bit will be 1
14. So the base address will be directly obtained from the Descriptor and the
offset address will be added to it to produce the Linear Address
80386 : Segment Translation
15. Before granting access to the desired location, a protection check is performed
based on the information given by the access right in the Descriptor

16. Several types of checks such as limit not exceeded, type of segment (data or
code), type of access (read/write/execute), privilege level etc carried out

17. If the checks are valid then access is granted, else a general protection fault
occurs

18. If paging is not implemented, then the 32 bit linear address is the final 32 bit
Physical Address
Descriptor Format
General Format of a Segment Descriptor
Descriptor Format
80386 | Page Translation
Paging Mechanism
80386 | Page Translation
80386 | Page Translation
1. The Virtual Memory space is divided into equal size blocks of 4KB called
“Pages”
2. The Physical Memory Space (also called Main Memory) is also divided into
equal size blocks of 4KB called Page Frames (also simply called pages)
3. As physical Memory is of 4GB and Page size is 4KB there are total 1 M
pages (2^20) in the Physical Memory
4. A page from Virtual Memory is loaded into any available page frame of
Physical Memory
5. Whenever a page is required to be accessed, the microprocessor first checks
if the desired page is present in the Physical Memory
a. If so, it is called a “Hit” and the operation is performed on the Physical Memory
6. A “Page Fault” (MISS) occurs when the desired page is not present in the
Physical Memory
80386 | Page Translation
7. On a Page Fault the desired page is loaded from virtual memory into any
available page frame of Physical Memory

8. If no page frame is available, then a “Page Replacement” is performed by

replacing an old page from the Physical Memory with the new desired page from
the Virtual Memory. Various algorithms like FIFO, LRU or LFU are used to
determine which page of the physical memory must be replaced

9. Once the page to be replaced is decided, a “dirty bit” is checked to determine if

the page is modified in the Physical Memory

10. If Dirty Bit = 1, then the page has been modified (is “Dirty”) and hence must be
copied back into Virtual Memory before being replaced else the modified
information will be lost
80386 | Page Translation
11. If Dirty bit = 0, then the page is not modified and hence can be directly
replaced without being copied back into Virtual Memory

12. Since a page of Virtual Memory can be loaded into any page frame of Physical
Memory, a “page Table” is required to give the mapping between Virtual Memory
page number and Physical Memory Page frame number

13. Simply speaking the Page Table tells which page of Virtual Memory is Present
in which page of Physical Memory

14. But since there are too many page frames in the Physical Memory (2^20 ie 1
MB) the page table will become too large and searches will become extremely
slow

15. Hence mechanism is further subdivided

80386 | Page Translation
16. Instead of having straight 1MB entries in the Page table, there are 1K (2^10)
entries in a page table and there are 1K such page tables

17. (2^20 = 2^10 * 2^10)

18. Each page table i of 4KB and ha 1K “page table entries” (PETs) each of size 4
bytes. Each PTE gives information about a Page Frame

19. The PTE has following information

a. 20 bit page frame address

b. D: Dirty Bit
c. A: Accessed Bit
d. U/S: User or Supervisor and R/W: Read or Read and Write
e. P: Present Bit
80386 | Page Translation
20. Information about all the page tables is stored in the “Page Directory”

21. The Page directory is of 4KB and has 1K “Page Directory Entries” (PDE) each
of size 4 bytes. Each PDE gives information about a Page Table

22. The PDE has following information:

a. 20 bit page table address : Gives the upper 20 bits of the starting address of
the corresponding page table. Lower 12 bits are 0..0 as the page table is of
4KB aligned location
b. D: Dirty Bit
c. A: Accessed Bit
d. U/S: User or Supervisor and R/W: Read or Read and Write
e. P: Present Bit
80386 | Page Translation
23. The Page Directory is of 4KB and begins from a 4KB aligned location

24. The Address of the Page directory is given by the PGBR (Page Directory Base
Register) field in CR3.

25. The 32 bit Linear Address can be divided into 3 parts

The higher 10 bits select one PDE out of 1K PDEs in the page directory

This gives the starting address in the page table

The next 10 bits select one PTE out of 1K PTEs in the page table

This gives the starting address of the page frame

Finally, the lowest 12 bits (Offset) select a location within the 4KB page
80386 | Page Translation
26. This means, to access any location, microprocessor must first access a PDE
in the page directory then a PTE in the page table, then access the page. This can
makes the process very slow. To speed up the process a “Translation Look-Aside
Buffer” is used (called TLB)

27. The TLB is an on chip cache which stores 32 most recently used PTEs and
PDEs. This makes subsequent access to these pages (whose information is
cached in the TBL) much faster as there is no need to access the Page directory
and the Page table.

28. Microprocessor can directly obtain the starting address of the page frame from
the TLB and hence directly access the page. Due to Principle of “Locality of
Reference” most systems get a Hit ratio of > 98% on the TLB, thus making the
operations very fast
80386 | Page Translation
80386 | Page Translation