Chapter 16

Instruction-Level Parallelism and Superscalar

processors
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 Table of contents

1. 2. 3. 4.
OVERVIEW DESIGN ISSUES PENTINUM 4 ARM COTEX-A8
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 Table Of Contents

01. 02. 03.

About Us Our Projects Stats & Numbers

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01.
Overview
Superscalar
Refers to a machine that is
designed to improve the In most applications the
Term first coined in 1987 performance of the bulk of the operations are
execution of scalar on scalar quantities
instructions

Essence of the approach is Concept can be further

Represents the next step in
the ability to execute exploited by allowing
the evolution of high-
instructions independently instructions to be executed
performance general-
and concurrently in in an order different from
purpose processors
different pipelines the program order
 SUPERSCALAR ORGANIZATION
ORDINARY SCALAR ORGANIZATION
Comparison of
superscalar
and super pipeline
Approaches
About Us

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 Constraints
• Instruction level parallelism
• Refers to the degree to which the instructions of a program can be
executed in parallel
• A combination of compiler based optimization and hardware techniques
can be used to maximize instruction level parallelism
• Limitations:
• True data dependency
• Procedural dependency
• Resource conflicts
• Output dependency
• Antidependency
02.
Design issues
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 Instruction level parallelism and machine
parallelism

Instruction level parallelism Machine parallelism

• Instructions in a sequence are dependent • Ability to take advantage of instruction
• Execution can be overlapped level parallelism
• Governed by data and procedural • Governed by number of parallel pipelines
dependency
 Instruction issue policy
Instruction issue Instruction issue policy

• Refers to the process of initiating instruction execution in • Refers to the protocol used to issue instructions
the processor’s functional units • Instruction issue occurs when instruction moves from the
decode stage of the pipeline to the first execute stage of
the pipeline

Superscalar instruction issue policies can be

3 types of orderings are important grouped into the following categories

• The order in which instructions are fetched • In-order issue with in-order completion
• The order in which instructions are executed • In-order issue with out-of-order completion
• The order in which instructions update the contents of • Out-of-order issue with out-of-order completion
register and memory locations
Superscalar instruction
issue and completion
policies
Organization for out-of-order issue with out-
of-order completion
Register renaming
Output and antidependencies occur
because register contents may not reflect
the correct ordering from the program

May result in a pipeline stall

Registers allocated dynamically

Speedups of various machine organizations without
procedural dependencies
03. Stats &
Numbers
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 Branch prediction
• Any high-performance pipelined machine must address the issue of dealing with
branches

• Intel 80486 addressed the problem by fetching both the next sequential instruction after
a branch and speculatively fetching the branch target instruction

• RISC machines:
• Delayed branch strategy was explored
• Processor always executes the single instruction that immediately follows the branch
• Keeps the pipeline full while the processor fetches a new instruction stream

• Superscalar machines:
• Delayed branch strategy has less appeal
• Have returned to pre-RISC techniques of branch prediction
Conceptual depiction of
superscalar processing
 Superscalar implementation
• Key elements:
• Instruction fetch strategies that simultaneously fetch multiple instruction
• Logic for determining true dependencies involving register values, and mechanisms
for communicating these values to where they are needed during execution
• Mechanisms for initiating, or issuing, multiple instructions in parallel
• Resources for parallel execution of multiple instructions, including multiple
pipelined functional units and memory hierarchies capable of simultaneously
servicing multiple memory references
• Mechanisms for committing the process state in correct order
 Branch prediction

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